Pressure sensor having a chamber and a method for fabricating the same

• US 20070275494A1
• Filed: 05/03/2007
• Published: 11/29/2007
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: InvenSense International, LLC
• Original Assignee: Sensirion Holding AG
• Inventors: Mayer, Felix, Streiff, Matthias, Buhler, Johannes, Sunier, Robert
• Granted Patent: US 7,704,774 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A pressure sensor is manufactured by joining two wafers, the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer, which is covered by the silicon layer of the second wafer to form a cavity. Part or all of the substrate of the second wafer is removed to forming a membrane from the silicon layer. Alternatively, the cavity can be formed in the second wafer. The second wafer is electrically connected to the circuitry on the first wafer. This design allows to use standard CMOS processes for integrating circuitry on the first wafer.

Claims

1. A method for fabricating a pressure sensor comprising the steps of

providing a first wafer comprising a base substrate of silicon with integrated circuitry integrated thereon and at least one material layer deposited on said base substrate,

providing a second wafer,

manufacturing a recess in said first wafer by locally removing or omitting said material layer,

mounting said second wafer, or a chip prepared from said second wafer, on said first wafer, and

electrically connecting said second wafer to said circuitry on said first wafer,

wherein said recess does not reach into said base substrate.

2. The method of claim 1 wherein said second wafer comprises a handle substrate, a silicon layer and an insulating layer between said handle substrate and said silicon layer.

3. The method of claim 2 wherein said silicon layer is positioned to form at least part of deformable membrane for sensing a pressure.

4. The method of claim 1 wherein said second wafer comprises a cavity closed by said membrane.

5. The method of claim 4 comprising the steps of forming a first electrical contact between said circuitry and said handle substrate and a second electrical contact between said circuitry and said membrane.

6. The method of claim 4 comprising the step of forming said cavity at least partially by forming a recess in said handle substrate.

7. The method of claim 4 wherein said cavity comprises a first chamber and a second chamber, the first chamber having smaller volume and smaller height than the second chamber, wherein said deformable membrane covers said first chamber.

8. The method of claim 1 comprising the step of removing at least part, and in particular all, of said handle substrate of said second wafer after mounting said second wafer on said first wafer.

9. The method of claim 8 comprising the step of removing at least part of said handle substrate at least down to said insulating layer.

10. The method of claim 1 comprising the step of mounting said second wafer to said first wafer with said silicon layer facing said first wafer.

11. The method of claim 1 comprising the step of mounting said second wafer on said first wafer in such a manner that said silicon layer of said second wafer forms said membrane over said recess.

12. The method claim 1 wherein said material layer is a silicon oxide, silicon nitride, metal or polisilicon layer.

13. The method of claim 12 wherein said recess is formed over a conducting layer, in particular a metal layer on said first wafer.

14. The method of claim 1 comprising the steps of

preparing a contact window on said first wafer,

forming or placing an edge of said second wafer at said contact window, and

applying a metal layer contacting said contact window to said edge.

15. The method of claim 1 comprising the steps of

preparing at least one contact window on said first wafer, and

placing said second wafer on said first wafer with a conducting material arranged between said second wafer and said contact window.

16. The method of claim 1 wherein said second wafer is a SOI wafer with said handle substrate being a silicon substrate.

17. The method of claim 1 wherein said integrated circuitry is manufactured using a CMOS process or a bipolar process.

18. The method of claim 1 further comprising the steps of

forming a cavity between said first and said second wafer,

removing material from said first wafer from a side opposite to said second wafer with a membrane formed by said first wafer remaining for closing said cavity.

19. The method of claim 18 wherein a passivation layer is applied from said second side to said first wafer.

20. The method of claim 18 comprising the step of locally etching off part of said second wafer,

and in particular wherein second wafer comprises a silicon top layer, an insulating layer and a handle substrate with the insulating layer being arranged between said top layer and said handle substrate, and, wherein said second wafer is locally etched off thus that top layer extends laterally beyond handle substrate, thereby forming projections, which projections are then enclosed by a wafer interconnect layer.

21. The method of any of claim 18 comprising the step of forming a recess in said first wafer from a side opposite to said second wafer into said first wafer, with said membrane remaining between said cavity and said recess.

22. A method for fabricating a pressure sensor comprising the steps of

providing a first wafer comprising integrated circuitry thereon,

providing a second wafer,

mounting said second wafer, or a chip prepared from said second wafer, on said first wafer, thereby forming a cavity between said first and said second wafer, and

applying a sealing layer to a seam between the first and the second wafer after joining them, thereby closing said seam.

23. The method of claim 22 wherein said seam covered by said sealing layer extends around said cavity.

24. The method of claim 22 wherein said sealing layer is applied to an edge of said first or said second wafer.

25. The method of claim 24 wherein said edge is beveled.

26. The method of claim 22 wherein said sealing layer consists of at least one material selected from the group comprising metal, glass, SiN, SiO₂ and DLC.

27. A method for fabricating a pressure sensor comprising the steps of

providing a first wafer comprising integrated circuitry thereon,

providing a second wafer,

mounting said second wafer, or a chip prepared from said second wafer, on said first wafer, thereby forming a cavity between said first and said second wafer, and

after mounting said second wafer or said chip to said first wafer, evacuating said cavity through an opening.

28. The method of claim 27, wherein said opening extends through a window in said second wafer.

29. The method of any of the claims 27 or 28 comprising the step of closing said opening after evacuating said cavity.

30. The method of claim 29 wherein said opening is closed by a sealing layer that covers a seam between the first and the second wafer, wherein the seam covered by said sealing layer extends around said cavity.

31. A pressure sensor comprising

at least one substrate formed from a wafer and

a cavity covered by a deformable membrane,

wherein said cavity comprises a first and a second chamber, wherein said first chamber has a smaller volume and height than said second chamber and wherein said membrane extends at least partially over said first chamber.

32. The sensor of claim 31 further comprising a channel connecting said first to said second chamber.

33. The sensor of claim 31 wherein said first chamber is arranged between two conducting layers forming a measuring capacitor.

34. The sensor of claim 33 wherein one of said conducting layers is arranged at a bottom of said first chamber.

35. A differential pressure sensor comprising

a substrate,

a chamber arranged at a first side of said substrate,

a flexible membrane covering said chamber, and

a through-hole connected to said chamber and extending through said substrate.

36. The sensor of claim 35 wherein said through-hole is arranged laterally beside said cavity.

37. The sensor of any of the claims 35 or 36 wherein said chamber is arranged between two conducting layers forming a measuring capacitor.

38. The sensor of claim 37 wherein one of said layers is arranged in said membrane and the other at a bottom of said chamber.