Method of manufacturing semiconductor device

• US 20070275520A1
• Filed: 05/15/2007
• Published: 11/29/2007
• Est. Priority Date: 05/25/2006
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Suzuki, Kazushi
• Granted Patent: US 7,785,980 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/708 Mark formation
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.

Claims

1. A method of manufacturing a semiconductor device, which comprises the steps of:

forming, on a semiconductor substrate, a first interconnection comprising a gate electrode with a metal layer on a top face thereof and an insulating film on said metal layer;

forming, in an interval of said first interconnection, a contact plug made of a conductor;

forming, over the entire surface, an interlayer insulating film;

forming a metal plug which runs through said interlayer insulating film and connects with said contact plug; and

forming a metal interconnection on said metal plug;

wherein

said metal interconnection is formed so as to align with a position of said contact plug; and

an alignment mark that is to be used in lithography for aligning said metal interconnection with said contact plugs is formed, on the bottom face inside a mark hole which is formed in said interlayer insulating film, of a multi-layered film which comprises said conductor to constitute said contact plug and said insulating film formed on said gate electrode.

2. The method of manufacturing the semiconductor device according to claim 1, wherein:

said first interconnection constitutes a word line;

said contact plug constitutes a memory cell contact plug which is connected with the surface of the semiconductor substrate;

said metal plug constitutes a bit line contact plug which is connected with said memory cell contact plug; and

said metal interconnection constitutes a bit line.

3. The method of manufacturing the semiconductor device according to claim 1, wherein said alignment mark has a plurality of convex rectangular patterns formed inside said mark hole which is formed in said interlayer insulating film.

4. The method of manufacturing the semiconductor device according to claim 2, wherein said alignment mark has a plurality of convex rectangular patterns formed inside said mark hole which is formed in said interlayer insulating film.

5. The method of manufacturing the semiconductor device according to claim 1, wherein:

said insulating film consists of one selected from the group consisting of a single layer of a silicon oxide film, a single layer of a silicon nitride film, a single layer of a silicon oxynitride film and a multi-layered film comprising at least two of said single layers;

said conductive substance consists of a silicon film; and

said alignment mark consists of a multi-layered film comprising said silicon film and said insulating film.

6. The method of manufacturing the semiconductor device according to claim 2, wherein:

said insulating film consists of one selected from the group consisting of a single layer of a silicon oxide film, a single layer of a silicon nitride film, a single layer of a silicon oxynitride film and a multi-layered film comprising at least two of said single layers;

said conductive substance consists of a silicon film; and

said alignment mark consists of a multi-layered film comprising said silicon film and said insulating film.

7. The method of manufacturing the semiconductor device according to claim 3, wherein:

said insulating film consists of one selected from the group consisting of a single layer of a silicon oxide film, a single layer of a silicon nitride film, a single layer of a silicon oxynitride film and a multi-layered film comprising at least two of said single layers;

said conductive substance consists of a silicon film; and

said alignment mark consists of a multi-layered film comprising said silicon film and said insulating film.

8. The method of manufacturing the semiconductor device according to claim 4, wherein:

said insulating film consists of one selected from the group consisting of a single layer of a silicon oxide film, a single layer of a silicon nitride film, a single layer of a silicon oxynitride film and a multi-layered film comprising at least two of said single layers;

said conductive substance consists of a silicon film; and

said alignment mark consists of a multi-layered film comprising said silicon film and said insulating film.

9. The method of manufacturing the semiconductor device according to claim 3, wherein said alignment mark consisting of said multi-layered film comprising said conductor and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

10. The method of manufacturing the semiconductor device according to claim 4, wherein said alignment mark consisting of said multi-layered film comprising said conductor and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

11. The method of manufacturing the semiconductor device according to claim 5, wherein said alignment mark consisting of said multi-layered film comprising said silicon film and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

12. The method of manufacturing the semiconductor device according to claim 6, wherein said alignment mark consisting of said multi-layered film comprising said silicon film and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

13. The method of manufacturing the semiconductor device according to claim 7, wherein said alignment mark consisting of said multi-layered film comprising said silicon film and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

14. The method of manufacturing the semiconductor device according to claim 8, wherein said alignment mark consisting of said multi-layered film comprising said silicon film and said insulating film is formed, in the step of forming said mark hole, in a manner of self-alignment to a pattern of said silicon film.

15. A method of manufacturing the semiconductor device, which comprises the steps of:

(1) forming, on a semiconductor substrate, a gate insulating film, a first silicon film, a first metal layer and an insulating film, in succession;

(2) forming, on said insulating film, a plurality of rectangular patterns consisting of a second silicon film;

(3) forming, over the entire surface, an interlayer insulating film and then planarizing a surface of said formed interlayer insulating film;

(4) forming a mark hole in said interlayer insulating film, to expose a plurality of said rectangular patterns consisting of said second silicon film on the bottom face inside said mark hole;

(5) removing an exposed portion of said insulating film on the bottom face of said mark hole, with said second silicon film which is exposed in the form of rectangular patterns being used as a mask, to form an alignment mark consisting of said insulating film and said second silicon film;

(6) forming, over the entire surface, a metal interconnection layer; and

(7) forming, over the entire surface, a photoresist and then forming, on said metal interconnection layer, an interconnection pattern made of said photoresist on said metal interconnection layer with said alignment mark consisting of said insulating film and said second silicon film being used as a mask.