Source and Shadow Wear-Leveling Method and Apparatus

• US 20070276987A1
• Filed: 06/22/2007
• Published: 11/29/2007
• Est. Priority Date: 02/26/2004
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Lee, Charles, Chow, David, Luo, Jianjun, Tsu, Chris
• Granted Patent: US 7,818,492 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

Claims

1. An flash memory system comprising:

flash memory organized into a plurality of blocks of pages, for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address; and

a flash controller adapted to communicate with a host and the flash memory and including volatile memory configured to store a source-shadow table of logical addresses addressable by the physical addresses, the logical addresses identifying the blocks, by the controller, the table having an address mapping table and a property value table, the property value table including property values, each of which is associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table,

wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

2. An flash memory system, as recited in claim 1, wherein the predetermined group of blocks is dictated by an area of flash memory to which the host is frequently recently accessing.

3. An flash memory system, as recited in claim 1, wherein during power-up, the property values are used to construct the table to reflect the current status of the recent information stored in the predetermined group of blocks.

4. A flash memory system, as recited in claim 1, wherein the source block is identified by information having been stored in the first and last pages thereof and the property value associated with the source block is used to identify the source block accordingly.

5. A flash memory system, as recited in claim 1, wherein the shadow block is identified by information having been stored in the first page thereof and the property value associated with the shadow block is used to identify the shadow block accordingly.

6. A flash memory system, as recited in claim 1, wherein an empty block is identified by the first and last pages thereof indicating lack of information having been stored therein since the last erase operation thereon.

7. A flash memory system, as recited in claim 1, wherein a defective block is identified by having information stored in its first and last pages being indicative of that which does not match that of an empty, source or shadow blocks.

8. A flash memory system, as recited in claim 1, further including flag information included in the spare of the first and last pages of a corresponding block indicative of the identification of status of the block.

9. A flash memory system, as recited in claim 1, wherein each page includes four sections of data and four sections of corresponding spare.

10. A flash memory system, as recited in claim 9, wherein each of the four data sections is 512 bytes.

11. A flash memory system, as recited in claim 9, wherein each of the four spares is 16 bytes.

12. A flash memory system, as recited in claim 9, wherein corresponding spares of a data section are stored adjacent thereto.

13. A flash memory system, as recited in claim 9, wherein the spare are stored after the data sections.

14. A flash memory system, as recited in claim 1, wherein the flash memory is NAND flash memory.

15. A flash memory system, as recited in claim 1, wherein the flash memory is multi-level cell (MLC).

16. A flash memory system, as recited in claim 1, wherein the flash memory is single level cell (SLC).

17. An flash controller comprising:

a flash controller adapted to communicate with a host and a flash memory, the flash memory organized into a plurality of blocks of pages, for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address;

the controller including volatile memory configured to store a source-shadow table of logical addresses addressable by the physical addresses, the logical addresses identifying the blocks, by the controller, the table having an address mapping portion and a property value portion, the property value portion including property values, each of which is associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping portion,

wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

18. An flash controller, as recited in claim 17, wherein the predetermined group of blocks is dictated by an area of flash memory to which the host is frequently recently accessing.

19. An flash controller, as recited in claim 17, wherein during power-up, the property values are used to construct the table to reflect the current status of the recent information stored in the predetermined group of blocks.

20. A flash controller, as recited in claim 17, wherein the source block is identified by information having been stored in the first and last pages thereof and the property value associated with the source block identifies the source block accordingly.

21. A flash controller, as recited in claim 17, wherein the shadow block is identified by information having been stored in the first page thereof and the property value associated with the shadow block the shadow block being accordingly.

22. A flash controller, as recited in claim 17, wherein an empty block is identified by the first and last pages thereof indicating lack of information having been stored therein.

23. A flash controller, as recited in claim 17, wherein a defective block is identified by having information stored in its first and last pages being indicative of that which does not match that of an empty, source or shadow blocks.

24. A flash controller, as recited in claim 17, further including flag information included in the spare of the first and last pages of a corresponding block indicative of the identification of status of the block.

25. A flash controller, as recited in claim 17, wherein each page includes four sections of data and four sections of corresponding spare.

26. A flash controller, as recited in claim 25, wherein each of the four data sections is 512 bytes.

27. A flash controller, as recited in claim 25, wherein each of the four spares is 16 bytes.

28. A flash controller, as recited in claim 25, wherein corresponding spares of a data section are stored adjacent thereto.

29. A flash controller, as recited in claim 25, wherein the spare are stored after the data sections.

30. A method of wear-leveling used in a flash memory system comprising:

receiving information to be written into a block of flash memory, the flash memory organized into a plurality of blocks of pages, for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address;

determining whether the received block of information has been written thereto without having been erased since the last time it was written; and

upon determining that the received block of information has not been written thereto since it was last written, writing the received block of information into a “

source”

block within the flash memory, identified by a physical address; and

upon determining that the received block of information has been previously written, writing the received block of information into a “

shadow”

block, within the flash memory, identified by a physical address.

31. A method of wear-leveling, as recited in claim 30, further including the steps of powering up the flash memory system, detecting “

shadow”

blocks by reading the spare of the first and last page of each block of the predetermined group of blocks, and reconstructing a source-shadow table based thereupon.