Methods and apparatus for providing simultaneous software/hardware cache fill
First Claim
Patent Images
1. A method, comprising:
- providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; and
providing a software implemented cache refill function operable to pre-load the at least one address translation table cache prior to a cache miss.
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Accused Products
Abstract
Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.
37 Citations
30 Claims
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1. A method, comprising:
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providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; and providing a software implemented cache refill function operable to pre-load the at least one address translation table cache prior to a cache miss. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. The method of claim 9, further comprising:
- permitting the application software to call operating system software of the processing system, which controls the hardware implemented cache refill circuit and the software implemented cache refill function to operate simultaneously in managing the at least one address translation table cache.
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10. A method, comprising:
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providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; providing a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refilling the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.
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11. A method, comprising:
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providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; providing a software implemented cache refill function also for managing the at least one address translation table cache and to pre-load the at least one address translation table cache prior to a cache miss; and simultaneously refilling the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An apparatus, comprising:
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at least one processor capable of being coupled to a memory; and an address translation circuit operable to translate a virtual address received from an external device into a physical address of the memory, wherein the address translation circuit includes; a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate the external address into the physical address; and a software implemented cache refill function also for managing the at least one address translation table cache, wherein at least one of;
(i) the hardware implemented cache refill circuit and the software implemented cache refill function are operable to simultaneously refill the at least one address translation table cache; and
(ii) the software implemented cache refill function is operable to pre-load the at least one address translation table cache prior to a cache miss. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. An address translation circuit, comprising:
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a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a memory space; and a software implemented cache refill function also for managing the at least one address translation table cache, wherein the hardware implemented cache refill circuit and the software implemented cache refill function are operable to simultaneously refill the at least one address translation table cache. - View Dependent Claims (27, 28, 29)
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30. A system, comprising:
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an internal memory space; at least one processor operatively coupled to the memory space; at least one segment table cache, each cache line of the segment table cache representing a different segment of the memory space; at least one page table cache, each entry in the page table cache including at least a portion of a physical address in the memory space and belonging to a group of entries representing a page in a given segment of the memory space; a hardware implemented cache refill circuit for managing the segment and page table caches; and a software implemented cache refill function also for managing the segment and page table caches, wherein at least one of;
(i) the hardware implemented cache refill circuit and the software implemented cache refill function are adapted to operate simultaneously; and
(ii) the software implemented cache refill function is operable to pre-load the segment and page table caches prior to a cache miss.
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Specification