Execution of a secured environment initialization instruction on a point-to-point interconnect system

• US 20070277223A1
• Filed: 05/26/2006
• Published: 11/29/2007
• Est. Priority Date: 05/26/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan J., Datta, Shamanna M.
• Granted Patent: US 8,973,094 B2
• Time in Patent Office: Days
• US Class Current: 726/2
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

Claims

1. A system, comprising:

a first processor to execute a secured enter instruction; and

a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

2. The system of claim 1, further comprising a point-to-point fabric to couple the first processor to the chipset.

3. The system of claim 2, further comprising a second processor coupled to the chipset by the point-to-point fabric, wherein the chipset is also to cause the second processor to enter the quiescent state during the execution of the secured enter instruction.

4. The system of claim 2, wherein the chipset is also to cause the system to enter the quiescent state in which only the first processor and the chipset communicate through the point-to-point fabric.

5. The system of claim 1, further comprising a trusted platform module, wherein the trusted platform module is accessible to the first processor during the quiescent state.

6. The system of claim 1, wherein the first processor is also to execute a secure initialization authenticated code module.

7. The system of claim 1, wherein the first processor is also to execute a secure virtual machine monitor module.

8. The system of claim 1, wherein the chipset includes an indicator accessible to the first processor to cause the chipset to cause the system to enter the quiescent state.

9. The system of claim 3, wherein:

the chipset includes;

an indicator accessible to the first processor to cause the chipset to cause the system to enter the quiescent state; and

a first storage location to indicate the identity of each processor in the system;

the second processor includes a second storage location to indicate that the second processor is connected to the point-to-point fabric; and

the first processor includes logic to verify that the identity of the second processor is indicated in the first storage location before accessing the indicator to cause the chipset to cause the system to enter the quiescent state.

10. A method, comprising:

starting to execute a secured enter instruction on a first processor coupled to a chipset through a point-to-point fabric;

causing the chipset to cause a second processor coupled to the point-to-point fabric to enter a quiescent state during the execution of a secured enter instruction.

11. The method of claim 10, further comprising the chipset maintaining a list of agents coupled to the point-to-point fabric.

12. The method of claim 11, further comprising reading a storage location in the second processor to identify the number of agents coupled to the point-to-point fabric through the second processor.

13. The method of claim 10, further comprising the first processor accessing a trusted platform module during the quiescent state.

14. The method of claim 13, further comprising executing a secure initialization authentication module.

15. The method of claim 14, further comprising reading an indicator in the chipset to verify that the quiescent state has been entered before executing the secure initialization authentication module.

16. The method of claim 13, further comprising executing a secure virtual machine monitor module.

17. The method of claim 16, further comprising reading an indicator in the chipset to verify that the quiescent state has been entered before executing the secure virtual machine monitor module.

18. The method of claim 10, further comprising causing the second processor to finish its event processing and drain its buffers before entering the quiescent state.

19. The method of claim 18, further comprising the second processor sending a signal to the chipset to acknowledge its entry into the quiescent state.

20. A processor, comprising:

secure enter logic to execute a first instruction to invoke secure operation initialization; and

interconnection messaging logic to cause a chipset to cause an agent coupled to the chipset through a point-to-point fabric to enter a quiescent state.