Nonvolatile semiconductor memory device

• US 20070278563A1
• Filed: 05/23/2007
• Published: 12/06/2007
• Est. Priority Date: 06/01/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takano, Tamae, Yamazaki, Shunpei, Tajima, Ryota, Tokuda, Atsushi
• Granted Patent: US 7,709,883 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An object is to provide a nonvolatile semiconductor memory device which is excellent in a writing property and a charge retention property. In addition, another object is to provide a nonvolatile semiconductor memory device capable of reducing writing voltage. A nonvolatile semiconductor memory device includes a semiconductor layer or a semiconductor substrate including a channel formation region between a pair of impurity regions that are formed apart from each other, and a first insulating layer, a plurality of layers formed of different nitride compounds, a second insulating layer, and a control gate that are formed in a position which is over the semiconductor layer or the semiconductor substrate and overlaps with the channel formation region.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor region containing a channel formation region between a pair of impurity regions;

a first insulating layer over the channel formation region;

a plurality of layers containing different nitride compounds over the first insulating layer; and

a control gate over the plurality of layers.

2. A nonvolatile semiconductor memory device according to claim 1, wherein one or more of the plurality of layers containing the different nitride compounds serve as a charge storage layer.

3. A nonvolatile semiconductor memory device according to claim 1, wherein one of the different nitride compounds is a germanium nitride compound.

4. A nonvolatile semiconductor memory device according to claim 3, wherein the germanium nitride compound is one selected from the group consisting of germanium nitride, germanium nitride to which oxygen is added, and germanium nitride to which oxygen and hydrogen are added.

5. A nonvolatile semiconductor memory device according to claim 1, wherein one of the different nitride compounds is a silicon nitride compound.

6. A nonvolatile semiconductor memory device according to claim 5, wherein the silicon nitride compound is one selected from the group consisting of silicon nitride, silicon nitride to which oxygen is added, and silicon nitride to which oxygen and hydrogen are added.

7. A nonvolatile semiconductor memory device according to claim 1, wherein each of the plurality of layers containing the different nitride compounds has a thickness of greater than or equal to 1 nm and less than or equal to 20 nm.

8. A nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer is a silicon oxide layer and contains nitrogen at an interface between the silicon oxide layer and the plurality of layers, or in the silicon oxide layer.

9. A nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer is formed in such a manner that a silicon oxide layer formed by oxidation of the semiconductor region by a plasma treatment is nitrided by a plasma treatment.

10. A nonvolatile semiconductor memory device according to claim 1, further comprising a second insulating layer formed between the plurality of layers containing the different nitride compounds and the control gate.

11. A nonvolatile semiconductor memory device according to claim 10, wherein the first insulating layer, the plurality of layers containing the different nitride compounds, the second insulating layer, and the control gate are stacked in a position that overlaps with the channel formation region.

12. A nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor region is a semiconductor layer formed over an insulating surface.

13. A nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor region is a semiconductor substrate.

14. A nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is incorporated in one selected from the group consisting of a digital camera, a mobile phone, a digital player and an electronic book.