Producing Thin Integrated Semiconductor Devices

• US 20070278653A1
• Filed: 06/01/2007
• Published: 12/06/2007
• Est. Priority Date: 06/01/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Brunnbauer, Markus, Fuergut, Edward, Kroeninger, Werner
• Granted Patent: US 7,674,654 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Thin integrated semiconductor devices are produced by being embedded in a molding compound matrix in such a way that a composite is formed. The semiconductor devices are first embedded in the matrix and then thinned after being embedded. The thin integrated semiconductor devices are singulated by forming separating cuts into the molding compound matrix between adjacent devices.

Claims

1. A method for producing thin devices having a thickness of no greater than 100 μ

m, the method comprising;

embedding a plurality of devices within a molding compound matrix to form a composite including the devices;

thinning the embedded devices to a desired thickness; and

singulating the embedded and thinned devices by providing separating cuts in the molding compound matrix between adjacent devices.

2. The method of claim 1, wherein the thin devices are integrated semiconductor devices.

3. The method of claim 1, further comprising:

applying a carrier film to a side of the composite before singulating the embedded and thinned devices, wherein the separating cuts in the singulating of the embedded and thinned devices do not extend through the carrier film.

4. The method of claim 1, wherein each embedded device includes opposing sides that are formed by a bevel cut such that the opposing sides are non-parallel with respect to each other.

5. The method of claim 1, wherein each of the embedded devices includes a front side with a metal layer disposed on the front side.

6. The method of claim 5, wherein the metal layer on the front side of each embedded device is coplanar with a corresponding front side of the molding compound matrix.

7. The method of claim 1, wherein the step of thinning comprises grinding a side of the molding compound matrix with the embedded devices over the entire surface area of the side.

8. The method of claim 1, wherein the step of thinning comprises performing a selective wet and/or dry etching of back sides of the embedded devices, wherein front sides of the embedded devices which oppose the back sides are coplanar with a corresponding front side of the molding compound matrix.

9. The method of claim 8, wherein the embedded and thinned devices are provided with a metal layer on the back sides after the thinning step.

10. The method of claim 9, wherein the providing of the back sides of the embedded and thinned devices with a metal layer comprises applying a seed layer over the surface areas of the back sides of the embedded and thinned devices and also a corresponding back side of the molding compound matrix.

11. The method of claim 10, wherein the seed layer is applied by a sputtering process or vacuum deposition process.

12. The method of claim 10, wherein the providing of the back sides of the embedded and thinned devices with a metal layer further comprises performing an electroless deposition of metal over the seed layer.

13. The method of claim 12, wherein the metal deposited over the seed layer comprises a nickel layer or a gold layer.

14. The method of claim 10, wherein the providing of the back sides of the embedded and thinned devices with a metal layer further comprises providing a photoresist mask over portions of the molding compound matrix before or after the application of the seed layer, wherein the photoresist mask prevents metal from being deposited on portions of the molding compound matrix.

15. The method as claimed in claim 9, further comprising:

thinning the metal layer applied on the back sides to a selected thickness.

16. The method of claim 1, wherein the singulating step comprises sawing sections of the molding compound matrix between adjacent devices.

17. The method of claim 1, wherein the singulating step comprises laser cutting sections of the molding compound matrix between adjacent devices.

18. The method of claim 2, further comprising:

performing a test of the thin integrated semiconductor devices embedded in the molding compound matrix.

19. The method of claim 2, wherein the singulating of the embedded and thinned devices yields individually packaged thin integrated semiconductor devices.

20. A composite comprising:

a plurality of semiconductor devices embedded in a molding compound matrix, wherein each semiconductor device has a thickness that is no greater than 100 μ

m, and each semiconductor device includes a front side that is coplanar with a corresponding front side of the molding compound matrix.

21. The composite of claim 20, wherein each semiconductor device includes opposing sides that form and edge with the front side and are non-parallel with respect to each other.