Top layers of metal for high performance IC's
First Claim
Patent Images
1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a first contact point of said first metallization structure, a second opening in said passivation layer exposing a second contact point of said first metallization structure;
a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first contact point, a fourth opening in said polymer layer exposing said second contact point, wherein said polymer layer has a thickness of greater than 2 microns; and
a second metallization structure over said polymer layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises a tungsten-containing metal structure and an electroplated metal structure over said tungsten-containing metal structure.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
103 Citations
20 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a first contact point of said first metallization structure, a second opening in said passivation layer exposing a second contact point of said first metallization structure;
a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first contact point, a fourth opening in said polymer layer exposing said second contact point, wherein said polymer layer has a thickness of greater than 2 microns; and
a second metallization structure over said polymer layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises a tungsten-containing metal structure and an electroplated metal structure over said tungsten-containing metal structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit chip comprising:
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a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a second metallization structure over said passivation layer and over said first and second pads, wherein said second metallization structure comprises a third pad connected to said first and second pads through said first and second openings, and wherein said second metallization structure comprises a tungsten-containing metal structure and an electroplated metal structure over said tungsten-containing metal structure; and
a metal bump over said third pad. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification