On-chip inductor using redistribution layer and dual-layer passivation

• US 20070279176A1
• Filed: 05/31/2006
• Published: 12/06/2007
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chen, Henry Kuo-Shun, Shiau, Guang-Jye, Ito, Akira
• Granted Patent: US 8,717,137 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01F 5/00 Coils superconducting coils H01F6/06; fixed inductances of the signal type H01F17/00
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.

Claims

1. An apparatus, comprising:

a metal layer;

a first passivation layer formed on the metal layer, the first passivation layer having a channel therethrough running to the metal layer;

a redistribution layer formed on the first passivation layer and formed in the channel, such that the redistribution layer contacts the metal layer;

a second passivation layer formed on the first passivation layer and the redistribution layer; and

a passive electrical element at least partially formed in the redistribution layer.

2. The apparatus of claim 1, wherein the passive electrical element comprises a multiple-layer passive electrical element, wherein:

a first layer is formed in the redistribution layer; and

a second layer is formed in the metal layer.

3. The apparatus of claim 1, further comprising:

a second metal layer;

a dielectric layer formed between the first metal layer and the second metal layer, the dielectric layer having a channel therethrough; and

a connection device formed between the first metal layer and the second metal layer and through the channel in the dielectric layer.

4. The apparatus of claim 3, wherein the passive electrical element comprises a multiple-layer passive electrical element, wherein:

a first layer is formed in the redistribution layer;

a second layer is formed in the first metal layer; and

a third layer is firmed in the second metal layer.

5. The apparatus of claim 1, wherein the passive electrical element comprises a transformer comprising first and second inductors, wherein the first and second inductors are formed in the redistribution layer.

6. The apparatus of claim 1, wherein the passive electrical element comprises a transformer comprising first and second inductors, wherein:

the first inductor is formed in the redistribution layer; and

the second inductor is formed in the metal layer.

7. The apparatus of claim 1, wherein the first and second passivation layers comprise a same material.

8. The apparatus of claim 1, wherein the first and second passivation layers comprise different materials.

9. The apparatus of claim 1, wherein the redistribution layer comprises a low resistivity metal.

10. The apparatus of claim 1, wherein the redistribution layer comprises aluminum or copper.

11. The apparatus of claim 1, wherein the passive electrical element comprises an inductor.

12. The apparatus of claim 1, wherein the first and second passivation layers comprise nitride.

13. The apparatus of claim 1, wherein one of the first and second passivation layers comprises nitride and another one of the first and second passivation layers comprises polyimide.

14. The apparatus of claim 1, wherein the redistribution layer is encapsulated between the first and second passivation layers.

15. The apparatus of claim 1, further comprising:

a plurality of additional metal layers;

a plurality of corresponding dielectric layers formed between the plurality of additional metal layers and between a top-most one of the plurality of the additional metal layers and the first metal layer;

a substrate located below a bottom-most one of the plurality of dielectric layers; and

a plurality of connecting devices connecting respective ones of the plurality of the additional metal layers, the substrate, and the first metal layer, the plurality of the connecting devices passing through vias in respective ones of the plurality of corresponding dielectric layers.

16. The apparatus of claim 1, wherein:

the first passivation layer comprises oxide, nitride, oxynitride, or polyimide; and

the second passivation layer comprises oxide, nitride, oxynitride, or polyimide.

17. The apparatus of claim 1, wherein the apparatus is located within a flip-chip.

18. The apparatus of claim 1, wherein the apparatus is located within a wirebond.

19. A method, comprising:

forming a metal layer;

forming a first passivation layer over the metal layer;

forming a via through the first passivation layer to the metal layer;

forming a redistribution layer on the first passivation layer and through the via in the first passivation layer, such that the redistribution layer contacts the first metal layer;

forming a second passivation layer over the redistribution layer; and

forming an inductor at least partially in the redistribution layer.

20. The method of claim 19, further comprising:

forming a first layer of the inductor in the redistribution layer; and

forming a second layer of the inductor in the metal layer.

21. The method of claim 19, further comprising:

forming another inductor in the metal layer, such that the inductor in the redistribution layer and the another inductor in the metal layer form a transformer.

22. The method of claim 19, further comprising forming another inductor in the redistribution layer, such that the inductor and the another inductor form a transformer.

23. The method of claim 19, further comprising:

forming additional metal layers;

wherein the inductor formed in the redistribution layer contains a first layer of a multiple layered inductor and further layers of the multiple layered inductor are formed in the metal layer and respective ones in the additional metal layers.