8T SRAM cell with higher voltage on the read WL

• US 20070279966A1
• Filed: 06/01/2006
• Published: 12/06/2007
• Est. Priority Date: 06/01/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore Warren
• Granted Patent: US 7,400,523 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Claims

1. Circuitry for writing to and reading from an SRAM cell core (102) of an array of SRAM cells, comprising:

a write circuit coupled to the SRAM cell core including a write transistor (118) having an electrical characteristic; and

a read circuit coupled to the SRAM cell core including a read transistor (207) and a read driver transistor (208) series coupled between a read bit line and a voltage source, the read driver transistor (208) having an electrical characteristic that differs from the electrical characteristic of a driver transistor (124, 126) of the core cell (102), wherein a gate of the read driver transistor (208) is coupled to an output (104) of the cell core (102).

2. The circuitry of claim 1, wherein the write transistor and the read transistor have different gate signals.

3. The circuitry of claim 1, wherein the electrical characteristic is a maximum drive current, the read driver transistor having a greater maximum drive current than the driver transistor of the core cell.

4. The circuitry of claim 1, wherein the electrical characteristic is one of a threshold voltage and a gate length, the read driver transistor having one of a lower threshold voltage and a shorter gate length than a driver transistor of the core cell.

5. The circuitry of claim 1, wherein the SRAM cell comprises:

a first inverter (112) comprising a first load transistor (120) and a first driver transistor (124), the first inverter having an input (106) and an output (104); and

a second inverter (114), cross-coupled with the first inverter, comprising a second load transistor (122) and a second driver transistor (126), the second inverter having an input (104) and an output (106).

6. The circuitry of claim 5, wherein the circuitry comprises a read transistor and a complementary read transistor.

7. The circuitry of claim 6, further comprising:

a read driver transistor, a gate of the read driver transistor coupled to the output (104) of the first inverter, and a drain of the read driver transistor coupled to a source of the read transistor; and

a complementary read driver transistor, a gate of the complementary read driver transistor coupled to the output (106) of the second inverter, and a drain of the complementary read driver transistor coupled to a source of the complementary read transistor.

8. The circuitry of claim 1, further comprising a Vss voltage and a Vss-array voltage, wherein the Vss-array voltage is applied to a source terminal of the core cells of the array.

9. The circuitry of claim 8, wherein the Vss-array voltage is greater than the Vss voltage.

10. The circuitry of claim 9, further comprising a Vss supply circuit having a voltage drop element connected between a source terminal of the core cell of the array (Vss-array) and a source voltage (Vss).

11. The circuitry of claim 10, wherein the voltage drop element is a transistor connected as a diode.

12. The circuitry of claim 8, wherein Vss is applied to a write bitline driver circuit used to drive the write bit line.

13. The circuitry of claim 1, wherein the gate of the read transistor is connected to a read word line associated with a row of cells, the read word line operable to control access to the cells in the row during a read operation.

14. An SRAM cell comprising:

a pair of cross-coupled inverters supplied by a voltage VDD;

a write transistor gated by a write word line and coupled between the output of one of the cross-coupled inverters and a write bit-line; and

a read transistor gated by a read word line and coupled between a read bit-line and a read driver transistor, wherein the read driver transistor is coupled between the read transistor and a source voltage, and is gated by an output of one of the cross-coupled inverters, and wherein the read driver transistor and a driver transistor of the core cell have an electrical characteristic that differs.

15. The SRAM cell of claim 14, wherein the write word line is separate from the read word line.

16. The SRAM cell of claim 14, wherein the electrical characteristic is a maximum drive current, the read transistor having a greater maximum drive current than the write transistor.

17. The SRAM cell of claim 14, wherein the electrical characteristic is one of a threshold voltage and a gate length, the read driver transistor having one of a lower threshold voltage and a shorter gate length than the driver transistor of one of the cross-coupled inverters.

18. The SRAM cell of claim 14, wherein the read driver transistor and a driver transistor of one of the cross-coupled inverters are formed adjacent to each other on a semiconductor substrate and have a common gate structure.

19. The SRAM cell of claim 14, wherein the read transistor has a lower threshold voltage or a shorter gate length than the write transistor.

20. An integrated circuit comprising an SRAM, said SRAM comprising:

an array of SRAM cells arranged in rows and columns;

a write word line associated with a row, the write word line operable to control access to cells in the row for write operations but not read operations;

a read word line associated with a row, the read word line operable to control access to cells in the row for read operations;

a write bit-line associated with a column operable to provide input to the cells in the column for write operations; and

a read bit-line associated with the column operable to receive output from cells in the column during read operations;

wherein the read word line is operable to be driven to a higher voltage during read operations than the write word line voltage is during write operations.

21. The integrated circuit of claim 20, wherein the read word line is driven above Vdd during a read operation.

22. The integrated circuit of claim 20, wherein the write word line is driven to a voltage that is below Vdd during a write operation.

23. The integrated circuit of claim 20, wherein the read bit line has a voltage substantially equal to a source voltage of the read driver transistor when not being accessed.

24. An integrated circuit comprising an SRAM, said SRAM comprising:

an array of SRAM cells arranged in rows and columns;

a write word line associated with a row, the write word line operable to control access to cells in the row for write operations;

a read word line associated with a row, the read word line operable to control access to cells in the row for read operations;

a write bit-line associated with a column operable to provide input to the cells in the column for write operations;

a read bit-line associated with the column operable to receive output from cells in the column during read operations; and

a write assist circuit operable to enable a write operation.

25. The integrated circuit of claim 24, wherein the read word line is separate from the write word line.

26. The integrated circuit of claim 25, wherein the write assist circuit is operable to enable a write operation, which permits the use of a write word line voltage that is lower than would cause upset of a cell in the associated row of cells, wherein the voltage applied to the write word line during write operations is lower than the voltage applied to the read word line during read operations.

27. The integrated circuit of claim 25, wherein the write assist circuit permits the use of a write word line voltage that is substantially the same as the read word line voltage.

28. The integrated circuit of claim 24, wherein the read word line is driven to a higher voltage for a read operation than the write word line is driven to for a write operation.

29. The integrated circuit of claim 24, wherein the write assist circuit comprises a voltage drop element connected between the source voltage of a write bit line driver and the source voltage of a memory cell.

30. The integrated circuit of claim 29, wherein the voltage drop element is a transistor connected as a diode.