Non-Volatile Memory Embedded In A Conventional Logic Process And Methods For Operating Same

• US 20070279987A1
• Filed: 06/02/2006
• Published: 12/06/2007
• Est. Priority Date: 01/26/2006
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Leung, Wingyu, Fang, Gang-feng
• Granted Patent: US 7,382,658 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

Claims

1. A non-volatile memory system comprising:

an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type;

a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding row; and

a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column.

2. The non-volatile memory system of claim 1, further comprising a well bias control circuit configured to independently bias the dedicated well regions.

3. The non-volatile memory system of claim 1, wherein the first set of control lines extend in parallel with the well regions along a first axis.

4. The non-volatile memory system of claim 3, wherein the second set of control lines extend in parallel along a second axis, perpendicular to the first axis.

5. The non-volatile memory system of claim 1, further comprising a third set of control lines, wherein each of the control lines in the third set is coupled to the diffusion region of each capacitor structure in a corresponding row.

6. The non-volatile memory system of claim 1, further comprising programming means for inducing band-to-band tunneling in selected access transistors in a selected row of the array, thereby programming the non-volatile memory cells that include the selected access transistors.

7. The non-volatile memory system of claim 6, wherein the programming means further comprises means for preventing band-to-band tunneling in non-selected access transistors in the selected row of the array by controlling a bias voltage applied to the drains of these non-selected access transistors.

8. The non-volatile memory system of claim 6, wherein the programming means further comprises means for preventing band-to-band tunneling in access transistors in non-selected rows of the array by controlling bias voltages applied to the well regions associated with these non-selected rows.

9. The non-volatile memory system of claim 6, wherein the programming means is configured to induce the band-to-band tunneling by controlling the junction voltage between the drain and well region of the selected access transistors.

10. The non-volatile memory system of claim 9, wherein the junction voltage is about 5 Volts.

11. The non-volatile memory system of claim 1, further comprising erase means for inducing Fowler-Nordheim tunneling in all of the access transistors in the array, thereby simultaneously erasing all of the non-volatile memory cells in the array.

12. A non-volatile memory system comprising:

an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type;

a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding column; and

a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column.

13. The non-volatile memory system of claim 12, further comprising a well bias control circuit configured to independently bias the dedicated well regions.

14. The non-volatile memory system of claim 12, wherein the first set of control lines and the second set of control lines extend in parallel along a first axis.

15. The non-volatile memory system of claim 14, wherein the well regions extend in parallel along a second axis, perpendicular to the first axis.

16. The non-volatile memory system of claim 12, further comprising a third set of control lines, wherein each of the control lines in the third set is coupled to the diffusion regions of each capacitor structure in a corresponding row.

17. The non-volatile memory system of claim 12, further comprising programming means for inducing band-to-band tunneling in selected access transistors in a selected row of the array, thereby programming the non-volatile memory cells containing the selected access transistors.

18. The non-volatile memory system of claim 17, wherein the programming means further comprises means for preventing band-to-band tunneling in non-selected access transistors in the selected row of the array by controlling a bias voltage applied to the drains of these access transistors.

19. The non-volatile memory system of claim 17, wherein the programming means further comprises means for preventing band-to-band tunneling in access transistors of non-volatile memory cells in non-selected rows of the array by controlling the bias voltages applied to the well regions of these non-selected rows.

20. The non-volatile memory system of claim 17, wherein the programming means is configured to induce the band-to-band tunneling by controlling the junction voltage between the drain and well region of the selected access transistors.

21. The non-volatile memory system of claim 20, wherein the junction voltage is about 5 Volts.

22. The non-volatile memory system of claim 12, further comprising erase means for inducing Fowler-Nordheim tunneling in all of the access transistors of the array, thereby simultaneously erasing all of the non-volatile memory cells in the array.

23. A method comprising:

programming selected non-volatile memory cells in a selected row of an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, and a floating gate electrode common to the access transistor and the capacitor structure, and wherein the programming is implemented by band-to-band tunneling into the floating gate electrodes of the selected non-volatile memory cells; and

preventing programming of non-selected non-volatile memory cells in the selected row of the array, wherein the step of preventing programming is implemented by controlling a bias voltage applied to a source/drain region of the access transistor of each non-selected non-volatile memory cell in the selected row.

24. The method of claim 23, further comprising:

preventing programming of non-volatile memory cells in non-selected rows of the array by controlling a bias voltage applied to dedicated well regions associated with the non-selected rows, wherein the access transistors in each row are fabricated in a corresponding dedicated well region.

25. The method of claim 24, wherein the step of preventing programming of non-volatile memory cells in the non-selected rows further comprising controlling a bias voltage applied to word lines associated with the non-selected rows, wherein the diffusion regions of the capacitor structures in each row are coupled to a corresponding word line.

26. The non-volatile memory system of claim 23, further comprising implementing the band-to-band tunneling within each of the selected non-volatile memory cells by controlling a junction voltage between a source/drain region of each of the access transistors of the selected non-volatile memory cells and a well region in which each of the access transistors of the selected non-volatile memory cells is fabricated.

27. The method of claim 26, further comprising biasing the junction voltage at about 5 Volts.

28. The method of claim 23, further comprising simultaneously erasing all of the non-volatile memory cells in the array by inducing Fowler-Nordheim tunneling in all of the access transistors in the array.

29. A non-volatile memory system comprising:

a non-volatile memory cell consisting of an NMOS transistor and a PMOS capacitor sharing a floating gate;

means for injecting electrons into the floating gate using a Fowler-Nordheim tunneling mechanism; and

means for injecting holes into the floating gate

using a band-to-band tunneling mechanism.

30. The non-volatile memory system of claim 29, wherein the means for injecting electrons into the floating gate are configured to induce electrons to tunnel from a channel of the NMOS transistor into the floating gate.

31. The non-volatile memory system of claim 29, wherein the means for injecting holes into the floating gate are configured to induce holes to tunnel from a drain junction of the NMOS transistor into the floating gate.

32. The non-volatile memory system of claim 29, further comprising one or more input/output transistors, each having a gate oxide layer, wherein the NMOS transistor and PMOS capacitor further include a gate oxide layer having a thickness substantially the same as a thickness of the gate oxide layer of the input/output transistors.

33. The non-volatile memory system of claim 32, wherein the non-volatile memory system is fabricated with a conventional logic process having one and only one polysilicon layer, wherein the floating gate is fabricated from the polysilicon layer.

34. A non-volatile memory system comprising:

a non-volatile memory cell consisting of an NMOS transistor and a PMOS capacitor sharing a floating gate;

means for injecting holes into the floating gate using a gate assisted band-to-band tunneling mechanism; and

means for injecting electrons into the floating gate using a channel-hot-electron mechanism.

35. The non-volatile memory system of claim 34, further comprising one or more input/output transistors, each having a gate oxide layer, wherein the NMOS transistor and PMOS capacitor further include a gate oxide layer having a thickness substantially the same as a thickness of the gate oxide layer of the input/output transistors.