Non-Volatile Memory Embedded In A Conventional Logic Process And Methods For Operating Same
First Claim
1. A non-volatile memory system comprising:
- an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type;
a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding row; and
a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column.
4 Assignments
0 Petitions
Accused Products
Abstract
A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
-
Citations
35 Claims
-
1. A non-volatile memory system comprising:
-
an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type; a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding row; and a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A non-volatile memory system comprising:
-
an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type; a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding column; and a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A method comprising:
-
programming selected non-volatile memory cells in a selected row of an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, and a floating gate electrode common to the access transistor and the capacitor structure, and wherein the programming is implemented by band-to-band tunneling into the floating gate electrodes of the selected non-volatile memory cells; and preventing programming of non-selected non-volatile memory cells in the selected row of the array, wherein the step of preventing programming is implemented by controlling a bias voltage applied to a source/drain region of the access transistor of each non-selected non-volatile memory cell in the selected row. - View Dependent Claims (24, 25, 26, 27, 28)
-
-
29. A non-volatile memory system comprising:
-
a non-volatile memory cell consisting of an NMOS transistor and a PMOS capacitor sharing a floating gate; means for injecting electrons into the floating gate using a Fowler-Nordheim tunneling mechanism; and means for injecting holes into the floating gate using a band-to-band tunneling mechanism. - View Dependent Claims (30, 31, 32, 33)
-
-
34. A non-volatile memory system comprising:
-
a non-volatile memory cell consisting of an NMOS transistor and a PMOS capacitor sharing a floating gate; means for injecting holes into the floating gate using a gate assisted band-to-band tunneling mechanism; and means for injecting electrons into the floating gate using a channel-hot-electron mechanism. - View Dependent Claims (35)
-
Specification