Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

• US 20070281418A1
• Filed: 05/31/2006
• Published: 12/06/2007
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Hu, Yongzhong
• Granted Patent: US 7,855,422 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Claims

1. A semiconductor device comprising:

a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a conductive layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure.

2. The semiconductor device of claim 1 wherein:

said polysilicon layer is further differentially doped to form said resistor as a high sheet rho resistor of said semiconductor device.

3. The semiconductor device of claim 1 wherein:

said polysilicon layer further doped with transistor gate doping ions to form a gate for said transistor of said semiconductor device.

4. The semiconductor device of claim 1 wherein:

said transistor further comprising a gate polysilicon and said resistor further comprising a doped polysilicon resistor, wherein said gate polysilicon, said doped polysilicon resistor and said doped polysilicon layer functioning as a bottom conductive layer of said capacitor are formed by one polysilicon deposition process and disposed substantially on a same vertical level in said semiconductor device.

5. The semiconductor device of claim 1 wherein:

said capacitor and resistor are disposed on a field oxide layer.

6. The semiconductor device of claim 1 wherein:

said transistor further includes an electrostatic discharge (ESD) protection layer formed on top of a diffusion resistor layer connected to a source or a drain region of said transistor; and

said TiSi layer is further electrically connected to a tungsten plug filled in a trench opened through an inter-layer dielectric layer covering said semiconductor device.

7. The semiconductor device of claim 1 wherein:

said doped polysilicon layer of said capacitor comprising a N+ doped polysilicon layer to function as a bottom conductive layer.

8. The semiconductor device of claim 1 wherein:

said capacitor further comprising a spacer surrounding and insulating said doped polysilicon layer to function as a bottom conductive layer.

9. The semiconductor device of claim 1 wherein:

said top conductive layer of said capacitor further comprising a Ti/TiN layer to function as a top conductive layer and said Ti/TiN layer is electrically connected to a tungsten plug filling in a trench opened through an inter-layer dielectric (ILD0) layer covering said semiconductor device.

10. The semiconductor device of claim 7 wherein:

said doped polysilicon layer as a bottom conductive layer of said capacitor comprising a N+ doped polysilicon layer covered by a TiSi conductive layer in contact with a tungsten plug filling in a trench opened through an inter-layer dielectric layer covering said semiconductor device.

11. The semiconductor device of claim 1 wherein:

said resistor includes a high resistive element comprising a doped resistive polysilicon segment wherein both ends of said resistive polysilicon element comprising contact head segments comprising N+ doped segments on both ends of the polysilicon segment; and

said contact head segments are further in contact with a tungsten plug filling in a trench opened through an inter-layer dielectric layer covering said semiconductor device

12. The semiconductor device of claim 1 wherein:

said resistor further includes a spacer layer for surrounding and insulting said high resistive element from said capacitor.

13. A method of manufacturing a semiconductor device comprising:

depositing a polysilicon layer on top of a semiconductor substrate followed by patterning and doping said polysilicon layer into a transistor gate, a bottom conductive layer for a capacitor and a resistor segment; and

forming said capacitor by depositing and patterning an insulator layer to function as a capacitor dielectric layer on top of said bottom conductive layer of said capacitor followed by depositing, patterning and annealing a Ti/TiN layer as a conductive layer to form a top conductive layer for said capacitor thus forming said capacitor as a single polysilicon layer metal-insulator-polysilicon (MIP) structure.

14. The method of claim 13 wherein:

said step of depositing and patterning an insulator layer comprising a step of depositing and patterning a salicide block (SAB) layer to function as a capacitor dielectric layer on top of said bottom conductive layer of said capacitor.

15. The method of claim 13 wherein:

said step of depositing and patterning an insulator layer comprising a step of depositing and patterning a high temperature oxide (HTO) layers to function as a capacitor dielectric layer on top of said bottom conductive layer of said capacitor.

16. The method of claim 13 wherein:

said step of depositing and patterning an insulator layer comprising a step of depositing and patterning an silicon oxide-silicon nitride and silicon oxide (ONO) stack layers to function as a capacitor dielectric layer on top of said bottom conductive layer of said capacitor.

17. The method of claim 13 wherein:

said step of depositing and patterning an insulator layer comprising a step of depositing and patterning an silicon oxyntirde to function as a capacitor dielectric layer on top of said bottom conductive layer of said capacitor.

18. The method of claim 13 further comprising:

applying a local oxidation silicon (LOCOS) process to form a field oxide for depositing said polysilicon layer thereon for patterning said polysilicon layer into said bottom conductive layer for a capacitor and said resistor segment.

19. The method of claim 18 further comprising:

applying a high resistance dopant implant to increase the resistance of said polysilicon layer followed by a polysilicon annealing process.

20. The method of claim 19 further comprising:

applying a source/drain mask to carry out a source drain implant followed by applying an elevated temperature to activate a source and a drain regions.

21. The method of claim 20 wherein:

said step of carrying out a source drain implant further comprising a step of doping said transistor gate and doping a portion of said resistor segment to function as resistor contact region.

22. The method of claim 13 wherein:

said step of depositing and patterning an insulator layer to function as a capacitor dielectric layer further includes a step of depositing a salicide block (SAB) layer followed by patterning said SAB layer into said dielectric layer for said capacitor.

23. The method of claim 22 wherein:

said step of depositing and patterning said SAB layer further includes a step of patterning said SAB layer into an ESD segment.

24. The method of claim 22 wherein:

said step of depositing and patterning said SAB layer further includes a step of patterning said SAB layer into an insulation layer covering said resistor segment.

25. The method of claim 13 wherein:

said step of depositing, patterning and annealing said Ti/TiN layer further includes a step of forming head contact regions for said resistor segment and a contact region for said capacitor bottom formed by said polysilicon layer.

26. The method of claim 25 wherein:

said step of depositing, patterning and annealing said Ti/TiN layer further includes a step of removing an un-reacted Ti/TiN for patterning a top surface above said SAB layer of said capacitor to form said single polysilicon MIP structure.

27. The method of claim 25 further comprising:

applying a second rapid thermal activation process to form a TiSi2 layer to function as contacts for said drain and source regions, said top capacitor surface and said contact head of said resistor segment.

28. The method of claim 27 further comprising:

forming a first interlayer dielectric layer (ILD0) covering said semiconductor device and opening contact openings on top of said contacts composed of said TiSi2.

29. The method of claim 28 further comprising:

filling said contact openings with a tungsten contact plug for contacting said contacts formed with said TiSi2.