Advanced Multilayered Coreless Support Structures and their Fabrication

• US 20070281471A1
• Filed: 06/01/2006
• Published: 12/06/2007
• Est. Priority Date: 06/01/2006
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Amitec-Advanced Multilayer Interconnect Technologies Ltd.
• Inventors: Hurwitz, Dror, Farkash, Mordechay, Igner, Eva, Statnikov, Boris, Michaeli, Benny
• Granted Patent: US 7,682,972 B2
• Time in Patent Office: Days
• US Class Current: 438/638
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/205 : using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages:

• • I—Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and
  • II—Detaching the membrane from the sacrificial carrier to form a free standing laminated array, and a method of fabricating an electronic substrate based on such a membrane comprising at least the stages of:
  • (I) Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier;
  • (II) Detaching the membrane from the sacrificial carrier to form a free standing laminated array;
  • (V) Thinning and planarizing, and
  • (VII) Terminating.

Claims

1. A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages:

I—

fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and

II—

Detaching the membrane from the sacrificial carrier to form a free standing laminated array.

2. The method of claim 1, wherein stage I comprises the sub-steps of:

(I) Panel plating a barrier metal layer onto a sacrificial carrier;

(ii) Applying a seed layer of copper onto the barrier metal layer;

(iii) Applying, exposing and developing a photoresist layer onto the copper seed layer to form patterns;

(iv) Pattern plating copper vias into the photoresist patterns;

(v) Stripping away the photoresist layer leaving the upstanding copper vias, and

(vi) Laminating a dielectric material layer over the copper vias, such that the free standing membrane formed thereby comprises a copper via array in a dielectric matrix.

3. The method of claim 1, wherein stage I comprises the sub-steps of:

(I) Applying, exposing and developing a photoresist layer directly onto a sacrificial carrier to form a patterns;

(ii) Pattern plating a barrier metal into the patterns thus formed;

(iii) Pattern plating copper vias onto the pattern plated barrier metal;

(iv) Stripping away the photoresist layer and baring the copper vias, and

(v) Laminating a dielectric material layer over the bare copper vias, such that the free standing membrane formed thereby comprises a copper via array in a dielectric matrix.

4. A free standing via membrane comprising a via array in a dielectric fabricated by the method of claim 1.

5. A method of fabricating an electronic substrate comprising at least the stages of:

I—

Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier;

II—

Detaching the membrane from the sacrificial carrier to form a free standing laminated array;

V—

Thinning and planarizing;

VI—

Building-up, and

VII—

Terminating.

6. The method of claim 5, wherein the conductive vias are fabricated from copper applied by a plating technique selected from the list of electroplating and electroless plating.

7. The method of claim 5 wherein stage I comprises the sub-steps of:

(I) Panel plating a barrier metal layer onto a sacrificial carrier;

(ii) Applying a seed layer of copper onto the barrier metal layer;

(iii) Applying, exposing and developing a photoresist layer onto the copper seed layer to form patterns;

(iv) Pattern plating copper vias into the photoresist patterns;

(v) Stripping away the photoresist layer leaving the upstanding copper vias, and

(vi) Laminating a dielectric material layer over the copper vias;

And stage II comprises the sub-steps of

(vii) Removing the sacrificial carrier, and

(viii) Removing the barrier metal layer,

Such that the resulting electronic substrate comprises a copper structure in a dielectric matrix.

8. The method of claim 7, wherein the barrier metal layer has at least one of the following characteristics:

(a) the barrier metal layer is selected from the list of tantalum, tungsten, chromium, titanium, a titanium-tungsten combination, a titanium-tantalum combination, nickel, gold, nickel layer followed by gold layer, a gold layer followed by a nickel layer, tin, lead, tin layer followed by a lead layer, tin-lead alloy, and tin-silver alloy and is applied by a physical vapor deposition process;

(b) the barrier metal layer is selected from the list of nickel, gold, a nickel layer followed by gold layer, a gold layer followed by a nickel layer, tin, lead, a tin layer followed by a lead layer, tin-lead alloy, and tin-silver alloy and is applied by a plating method selected from the list of electroplating and electroless plating, and

(c) the barrier metal layer has a thickness in the range of 0.1 μ

m to 5 μ

m.

9. The method of claim 7, further comprising stage III of adding a metal feature layer and a further via layer to form an inner substructure comprising a center metal feature layer membrane surrounded by via layers, such that the electronic substrate built up therearound has an odd number of metal feature layers.

10. The method of claim 9 wherein stage III comprises the sub-steps of:

(a) applying, exposing and developing a photoresist layer onto the copper seed layer to form feature patterns;

(b) Pattern plating copper feature layer into the feature patterns;

(c) stripping away the photoresist layer,

(d) applying exposing and developing a second layer of photoresist to form via patterns;

(e) Pattern plating copper into the via patterns to form copper vias;

(f) stripping away the second layer of photoresist;

(g) etching the copper seed layer, and

(h) laminating a dielectric material layer over the bare copper vias and copper feature layers;

.

11. The method of claim 9, further comprising stage IV of adding a further inner feature layer followed by a further inner via layer to form an inner substructure comprising a central via layer surrounded by feature layers, such that the electronic substrate built up therearound has an even number of metal feature layers.

12. The method of claim 11 wherein stage IV of adding a further features layers and a further via layers, comprises the steps of:

(I) thinning and planarizing the laminated dielectric material layer applied in step (j) to expose the outer surface of the vias applied in step (e);

(k) applying adhesion metal layers onto the exposed outer surfaces of vias and laminated dielectric material layer therearound;

(l) applying copper seed layers onto the adhesion metal layers;

(m) applying, exposing and developing second feature layers of photoresist onto the copper seed layers to form second feature patterns;

(n) Pattern plating copper feature layer into the second feature patterns;

(o) stripping away the second feature layer of photoresist;

(p) applying exposing and developing a third via layers of photoresist to form third via patterns;

(q) applying copper into the third via patterns to form third layers of copper vias;

(r) stripping away the third layers of photoresist;

(s) etching away the copper seed layers and adhesion metal layers, and

(t) laminating a dielectric material layers thereover.

13. The method of claim 11 wherein the adhesion metal is selected from the list of titanium, chrome, and nickel chrome.

14. The method of claim 5, wherein stage I comprises the sub-steps of:

(I) Applying, exposing &

developing a photoresist layer directly onto a sacrificial carrier to form patterns;

(ii) Pattern plating a barrier metal into the patterns thus formed;

(iii) Pattern plating copper vias onto the pattern plated barrier metal;

(iv) Stripping away the photoresist layer and baring the copper vias;

(v) Laminating a dielectric material layer over the bare copper vias, and

Step II comprises the step of

(vi) Removing the sacrificial carrier,

Such that the resulting electronic substrate comprises a copper structure in a dielectric matrix having a layer of barrier metal included within the copper structure.

15. The method of claim 14, wherein the barrier metal layer has at least one of the following characteristics:

(a) the barrier metal layer is selected from the list of nickel, gold, a nickel layer followed by a gold layer, a gold layer followed by a nickel layer, tin, lead, tin layer followed by a lead layer, tin-lead alloy, and tin-silver alloy, and is applied by a plating method selected from the list of electroplating, electroless plating, and combinations of electroplating and electroless plating;

(b) the barrier metal layer has a thickness in the range of 0.1 μ

m to 5 μ

m.

16. The method of claim 14, further comprising stage III of adding a first metal feature layer and a second via layer to form an inner substructure comprising a center metal feature layer membrane surrounded by via layers, such that the electronic substrate built up therearound has an odd number of metal feature layers.

17. The method of claim 16, wherein stage III of adding a first metal feature layer and a second via layer to form an inner substructure comprising a center metal feature layer membrane surrounded by via layers, comprises the steps of:

(vii) applying an adhesion metal layer to surface exposed by step (vi), the exposed surface comprising ends of vias coated with barrier metal, surrounded by dielectric material;

(viii) applying a seed layer of copper onto the adhesion metal layer;

(ix) applying, exposing and developing a first feature photoresist layer to form feature patterns;

(x) Pattern plating copper layer into the feature patterns;

(xi) Stripping away the first feature photoresist layer;

(xii) Applying exposing and developing a second via layer of photoresist to form via patterns;

(xiii) Pattern plating copper into the second via patterns to form a second layer of copper vias;

(xiv) Stripping away the second via layer of photoresist;

(xv) Etching away the copper seed layer;

(xvi) Removing the adhesion metal layer, and

(xvii) Laminating a dielectric material layer over the exposed second layer of vias.

18. The method of claim 17 wherein the adhesion metal is selected from the list of titanium, chrome, and nickel chrome.

19. The method of claim 16 , further comprising stage IV of adding a second feature layer and a third via layer to form an inner substructure comprising two feature layers around a central via layer, such that the electronic substrate built up therearound has an even number of metal feature layers.

20. The method of claim 19 wherein stage IV of adding a further feature layers and a further via layers, comprises the steps of:

(xviii) Thinning and planarizing the laminated dielectric material layer applied in step (xvii), thereby exposing the outer surface of the via layer applied in step (xiii);

(xix) Applying an adhesion metal layer onto the exposed via surfaces and onto the laminated dielectric material therearound;

(xx) Applying a copper seed layer onto the adhesion layer;

(xxi) Applying, exposing and developing a further layer of photoresist to form feature patterns;

(xxii) Pattern plating copper into the feature patterns of step (xxi) to form a second feature layer;

(xxiii) Stripping away the further layer of photoresist of step (xxi);

(xxiv) Applying exposing and developing a further layer of photoresist to form third layer via patterns;

(xxv) Pattern plating copper into the third via patterns to form a third layer of copper vias;

(xxvi) Stripping away the further layer of photoresist;

(xxvii) Etching away the copper seed layer and the adhesion metal layer, and

(xxviii) Laminating a dielectric material layer thereover.

21. The method of claim 5 wherein the dielectric material layer is a fiber reinforced resin composite.

22. The method of claim 5, wherein the dielectric material layer comprises a resin selected from the list of thermoplastic resins, thermosetting polymeric resins and resins having mixed thermoplastic and thermosetting properties.

23. The method of claim 22, wherein the dielectric material layer further comprises inorganic particulate fillers and the dielectric material is further characterized by having at least one of the following characteristics:

(a) the inorganic particulate fillers comprise particles of a ceramic or glass;

(b) particle sizes of the order of single microns, and

(c) 15% to 30% of particulate filler by weight.

24. The method of claim 22, wherein the dielectric material is a fiber matrix composite material and further comprises fibers selected from the list of organic fibers and glass fibers as chopped fibers or continuous fibers arranged in cross-plied arrangements or as woven mats.

25. The method of claim 23 wherein the dielectric material layer is a prepreg comprising a fiber mat that is pre-impregnated with a partially cured polymeric resin.

26. The method of claim 5 wherein stage II of detaching the laminated columnar via structure from the sacrificial carrier to form a free standing laminated array comprises removing the sacrificial carrier away by an etching process.

27. The method of claim 5 wherein the stage of thinning and planarizing dielectric material layers, to expose outer via surfaces therebeneath, comprises a technique selected from the list of mechanically grinding, chemical mechanical polishing (CMP), dry etching and multiple stage processing using two or more of these techniques.

28. The method of claim 5, further comprising an additional stage VI, of building up feature layers and via layers on both sides of the membrane.

29. The method of claim 28, wherein additional stage VI comprises the steps of:

(a) Applying adhesion metal layers;

(b) Applying seed layers of copper onto the adhesion metal layers;

(c) Applying, exposing and developing first outer layers of photoresist onto copper seed layers to form patterns for first outer feature layers;

(d) Pattern plating first outer copper features into the first outer layers of photoresist patterns;

(e) Stripping away the first outer layers of photoresist;

(f) Applying, exposing and developing second outer layers of photoresist to form patterns for first outer via layers;

(g) Pattern plating first outer copper vias into second outer layers of photoresist patterns;

(h) Stripping away second outer layers of photoresist;

(l) Etching away the copper seed layers and adhesion metal layers;

(j) Laminating dielectric material layers over the exposed copper features and vias, and

(k) Thinning and planarizing the dielectric material layers until the outer faces of the vias are exposed.

30. The method of claim 29 wherein the adhesion metal is selected from the list of titanium, chrome, and nickel chrome.

31. The method of claim 29 wherein steps (a) to (k) are repeated, thereby building up additional outer layers.

32. The method of claim 5, wherein stage VII of terminating, comprises the steps of:

(I) Applying outer adhesion metal layers to outer layers of stacked structure;

(ii) Applying outer copper seed layers onto the outer adhesion metal layers;

(iii) Applying, exposing and developing outer photoresist layers to form patterns;

(iv) Pattern plating copper lines and pads features into outer layers of photoresist patterns;

(v) Stripping away the outer photoresist layers;

(vi) Applying exposing and developing terminal photoresist layers to selectively expose copper the pads;

(vii) Electroplating termination metal layers onto the exposed copper pads, said termination metal layers being fabricated from a metal selected from the list of nickel, gold, tin, lead, silver, palladium, and combinations and alloys thereof;

(viii) Stripping away the terminal photoresist layers;

(ix) Etching exposed copper seed layers and exposed adhesion metal layers, and

(x) Applying exposing and developing solder mask layers so to mask copper lines and expose termination metal layers.

33. The method of claim 5 wherein stage VII of terminating the electronic support structure comprises the steps of:

(I) applying outer adhesion metal layers to outer layers of stacked structure;

(ii) applying outer copper seed layers onto the outer adhesion metal layers;

(iii) Applying, exposing and developing outer photoresist layers to form patterns;

(iv) Pattern plating copper lines and pads features into outer layers of photoresist patterns;

(v) Stripping away the outer photoresist layers;

(vi) Etching exposed copper seed layers and exposed adhesion metal layers

(vii) Applying exposing and developing solder mask layers so to mask copper lines and expose copper pads.

(viii) Electroless plating termination layers onto exposed copper pads, said termination layers being fabricated from a metal selected from the list of nickel, gold, tin, lead, silver, palladium, nickel-gold, tin-silver, alloys and tarnish resistant polymer materials.

34. A structure fabricated by the method of claim 5, the structure having an even number of feature layers.

35. A structure fabricated by the method of claim 5, the structure having an odd number of feature layers.

36. A structure fabricated by the method of claim 5, the structure being substantially symmetrical.