Communication semiconductor integrated circuit device and wireless communication system

• US 20070281651A1
• Filed: 06/08/2007
• Published: 12/06/2007
• Est. Priority Date: 04/26/2002
• Status: Abandoned Application

• Current Assignee: Hirotaka Oosawa, Masumi Kasahara, Noriyuki Kurakami, Toshiya Uozumi
• Original Assignee: Hirotaka Oosawa, Masumi Kasahara, Noriyuki Kurakami, Toshiya Uozumi
• Inventors: Oosawa, Hirotaka, Kasahara, Masumi, Kurakami, Noriyuki, Uozumi, Toshiya
• Application Number:
  US11/808,285
• Publication Number:
  US 20070281651A1
• Time in Patent Office: Days
• US Class Current: 455/245.100
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained. Further, a control voltage closest to the set frequency is determined on the basis of the frequency difference and the frequency variable range of the selected band and the control voltage is applied to the oscillator to start oscillating operation. After that, a PLL loop is closed and locked.

Claims

1-22. -22. (canceled)

23. A semiconductor integrated circuit device for a radio communication device comprising:

a phase locked loop circuit which includes a phase detection circuit which detects a phase difference between a reference signal having a predetermined frequency and a feedback signal which is an output signal of the phase locked loop circuit, a signal generation circuit which generates a first voltage in response to phase difference information signals from the phase detection circuit, an oscillation circuit which generates the output signal responding to a voltage of a filter that is charged or discharged by the signal generation circuit and which generates the output signal in accordance with desired frequency information;

a measuring circuit which measures a frequency of the output signal and outputs first frequency information which includes the frequency of the output signal;

a band selection circuit which selects an oscillation frequency band from a plurality of frequency bands by comparing the desired frequency information and the first frequency information and which generates a band selection signal;

an initial voltage generating circuit which generates a second voltage based on the band selection signal; and

a switching circuit which elects the second voltage or the first voltage for supplying to the filter or the oscillation circuit,

wherein the switching circuit elects the second voltage at a beginning of operation of the phase locked loop circuit to perform a pull-in operation, and the switching circuit is switched to supply the first voltage to the oscillation circuit or the filter to lock the phase locked loop circuit after the pull-in operation.

24. A semiconductor integrated circuit device for a radio communication device according to claim 23,

wherein the second voltage is composed of a plurality of voltages and set step by step, and

wherein the initial voltage generating circuit selects one of the plurality of voltages as the second voltage for the oscillation circuit to oscillate with a desired frequency.

25. A semiconductor integrated circuit device for a radio communication device according to claim 23,

wherein the second voltage is supplied to the filter or the oscillation circuit when the measuring circuit measures the frequency of the output signal.

26. A semiconductor integrated circuit device for a radio communication device according to claim 23, further comprising a control circuit which controls switching of the switching circuit,

wherein at a time that the phase locked loop circuit is in an open loop state, the switching circuit is switched by the control circuit for supplying the second voltage to the oscillation circuit or the filter, so that the oscillation circuit is oscillated in accordance with the second voltage, and the measuring circuit measures the frequency in each of the oscillation frequency bands, and

wherein at a time that the phase locked loop circuit is a closed loop state, the switching circuit is switched by the control circuit for supplying the first voltage to the oscillation circuit or the filter, so that the oscillation circuit is oscillated at the desired frequency in accordance with the desired frequency information.

27. A semiconductor integrated circuit device for a radio communication device according to claim 26, further comprising a counter circuit which divides the frequency of the output signal and which is provided between the oscillation circuit and the phase detection circuit,

wherein the counter circuit also performs as the measuring circuit.

28. A semiconductor integrated circuit device for a radio communication device according to claim 27,

wherein the counter circuit includes:

a frequency divider capable of switching a frequency division ratio;

a first programmable counter capable of computing a value corresponding to a quotient obtained by dividing a frequency of a signal to be output from the oscillation circuit by a frequency of the reference signal and further dividing the resultant by one of plural frequency division ratios of the frequency divider; and

a second programmable counter capable of computing a value corresponding to a remainder of the division,

wherein the value computed by the first programmable counter is supplied to the band selection circuit as the first frequency information.

29. A semiconductor integrated circuit device for a radio communication device according to claim 23, further comprising:

a first mixer for mixing the output signal from the phase locked loop circuit or a signal obtained by dividing the frequency of the output signal with a reception signal, thereby obtaining a demodulated signal; and

a second mixer for mixing the output signal from the phase locked loop circuit or a signal obtained by dividing the frequency of the output signal with a transmission signal, thereby obtaining a signal of a frequency corresponding to a frequency difference.

30. A semiconductor integrated circuit device for a radio communication device according to claim 29, further comprising

a third mixer for mixing the output signal from the phase locked loop circuit with a detection signal of the power amplifier, thereby obtaining a frequency-converted signal.