Function-based virtual-to-physical address translation

• US 20070283123A1
• Filed: 06/05/2006
• Published: 12/06/2007
• Est. Priority Date: 06/05/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Vick, Christopher A., Paleczny, Michael H., Manczak, Olaf, Freeman, Jay R., Gustafson, Phyllis E.
• Granted Patent: US 7,822,941 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/683 Invalidation

Abstract

A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.

Claims

1. A method, comprising:

detecting invocation of a trap handler;

determining that said invocation of said trap handler was initiated in response to a failure to locate a valid virtual-to-physical address translation for a given virtual address;

in response to said determining, invoking a translation function to translate said given virtual address to a physical address;

wherein said translation function takes said given virtual address as an input; and

wherein said translation function determines said physical address without reference to a translation table.

2. The method of claim 1, wherein said translation function comprises one or more of:

an arithmetic operation, a logical operation, a modulus operation, a shift operation and a rotate operation.

3. The method of claim 1, wherein said invoking said translation function comprises executing program instructions configured to translate said given virtual address to said physical address.

4. The method of claim 1, wherein said invoking said translation function comprises address translation circuitry translating said given virtual address to said physical address.

5. The method of claim 1, wherein said invocation of said trap handler is initiated in response to a translation lookaside buffer (TLB) miss.

6. The method of claim 1, wherein said trap handler comprises program instructions configured to implement said translation function.

7. The method of claim 1, wherein said trap handler comprises program instructions configured to replace a second trap handler, wherein said second trap handler comprises one or more table look-up operations used in determining a translation from said given virtual address to said physical address.

8. The method of claim 1, wherein said given virtual address is within a first address range, and wherein the method further comprises:

detecting a second invocation of a trap handler;

determining that said second invocation of a trap handler was initiated in response to a failure to locate a valid virtual-to-physical address translation for a second virtual address, wherein said second virtual address is within a second address range; and

in response to said determining that said second invocation of a trap handler was initiated in response to a failure to locate a valid virtual-to-physical address translation for a second virtual address, invoking a second translation function to translate said second virtual address to a second physical address;

wherein said second translation function takes said second virtual address as an input;

wherein said second translation function determines said second physical address without reference to, a translation table.

9. The method of claim 1, wherein said given virtual address is accessed by a first plurality of instructions, and wherein the method further comprises:

detecting a second invocation of a trap handler;

determining that said second invocation of a trap handler was initiated in response to a failure to locate a valid virtual-to-physical address translation for a second virtual address, wherein said second virtual address is accessed by a second plurality of instructions;

invoking a second translation function to translate said second virtual address to a second physical address;

wherein said second translation function takes said second virtual address as an input;

wherein said second translation function determines said second physical address without reference to a translation table.

10. The method of claim 1, further comprising determining said translation function, wherein said determining said translation function comprises:

analyzing a memory organization, wherein said memory organization comprises one or more mappings from a virtual memory address space to a corresponding physical memory address space of a memory; and

computing a function to translate virtual memory addresses to physical memory addresses, dependent on said one or more mappings, such that said physical address determined by said function is equal to a physical address mapped to said given virtual address according to one of said one or more mappings.

11. The method of claim 10, further comprising reorganizing said memory prior to determining said translation function, wherein said reorganizing comprises one or more of:

reducing fragmentation of said memory, changing a page size, changing a segment size, and changing one or more mappings of a virtual address space to a physical address space.

12. The method of claim 1, further comprising analyzing performance of said translation function and dynamically determining a second translation function dependent on said analyzing.

13. A system, comprising:

a processor configured to support memory virtualization; and

a memory configured to communicate with said processor;

wherein said processor is further configured to;

detect an invocation of a trap handler;

determine that said invocation of a trap handler was initiated in response to a failure to locate a valid virtual-to-physical address mapping for translating a given virtual address to a physical address of said memory;

in response to said determining, invoke a translation function to translate said given virtual address to said physical address;

wherein said translation function takes said given virtual address as an input;

wherein said translation function determines said physical address without reference to a translation table; and

wherein said translation function comprises one or more of;

an arithmetic operation, a logical operation, a modulus operation, a shift operation and a rotate operation.

14. The system of claim 13, wherein to invoke said translation function, said processor is further configured to execute program instructions configured to translate said given virtual address to said physical address.

15. The system of claim 13, wherein said processor further comprises address translation circuitry, and wherein to invoke said translation function said address translation circuitry translates said given virtual address to said physical address.

16. The system of claim 13, wherein said invocation of said trap handler is initiated in response to a translation lookaside buffer (TLB) miss.

17. The system of claim 13, wherein said processor is further configured to:

analyze a memory organization, wherein said memory organization comprises one or more mappings from a virtual address space to a corresponding physical address space of said memory; and

determine said translation function, wherein said translation function is configured to translate virtual memory addresses to physical memory addresses, dependent on said analyzing, such that said physical address determined by said translation function is equal to a physical address mapped to said given virtual address according to one of said one or more mappings.

18. The system of claim 17, wherein said processor is further configured to re-organize said memory prior to determining said translation function, wherein to re-organize said memory said processor is configured to perform one or more of:

reducing fragmentation of said memory, changing a page size, changing a segment size, and changing one or more mappings of a virtual address space to a physical address space.

19. A processor configured to support memory virtualization, comprising:

a trap handler; and

an exception handler;

wherein said exception handler is configured to invoke said trap handler in response to a failure to locate a valid virtual-to-physical address mapping for translating a given virtual address to a physical address of a memory;

wherein said trap handler is configured to invoke a function to translate said given virtual address to said physical address, wherein said function takes said given virtual address as an input, wherein said function determines said physical address without reference to a translation table, and wherein said function comprises one or more of;

an arithmetic operation, a logical operation, a modulus operation, a shift operation and a rotate operation.

20. The processor of claim 19, further comprising a function determiner, wherein said function determiner is configured to:

analyze a memory organization, wherein said memory organization comprises one or more mappings from a virtual address space to a corresponding physical address space; and

determine said function, wherein said function is configured to translate virtual memory addresses to physical memory addresses dependent on said analyzing, such that said physical address determined by said translation function is equal to a physical address mapped to said given virtual address according to one of said one or more mappings.