Method and system for multi-processor initialization in information handling systems

• US 20070283137A1
• Filed: 06/01/2006
• Published: 12/06/2007
• Est. Priority Date: 06/01/2006
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Marslett, Charles, Ueltschey, Charles Marion
• Granted Patent: US 7,600,109 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

Methods and systems are disclosed for multi-processor initialization in an information handling system with two or more application processors (APs). One of the APs is configured to be a boot strap processor (BSP) that communicates with the other APs to initialize them prior to initialization of main memory. A basic input output system (BIOS) can be coupled to the APs and can be configured to hold BSP code and AP code used for initialization. APs are then discovered and initialized before the main memory of the system is initialized.

Claims

1. A method for multi-processor initialization in an information handling system, comprising:

providing two or more application processors (APs) within an information handling system;

configuring one of the APs to be a boot strap processor (BSP) for the information handling system;

operating the BSP to communicate with the other APs to initialize the APs prior to initialization of main memory; and

operating each AP to communicate with the BSP for AP initialization.

2. The method of claim 1, further comprising providing a basic input output system (BIOS) within the information handling system and configuring the BIOS to have BSP code and AP code utilized by the BSP and the APs to perform the operating steps.

3. The method of claim 1, further comprising utilizing shared memory to communicate between the BSP and the APs for the operating steps.

4. The method of claim 3, wherein the shared memory is not part of main memory.

5. The method of claim 4, further comprising utilizing a plurality of registers for the shared memory, the registers being accessible to the BSP and each of the APs.

6. The method of claim 3, further comprising sending a command from the BSP to the other APs to cause the APs to each attempt to access a first location in the shared memory to write identification data.

7. The method of claim 6, further comprising operating the BSP to read identification data for one of the APs from the first location in the shared memory and to move the identification data to a second location in the shared memory.

8. The method of claim 7, further comprising operating the AP to read the second location in shared memory to determine if its identification data is in the second location and if so, to write initialization pass or fail information to a third location in the shared memory

9. The method of claim 8, further comprising operating the BSP to read the third location in shared memory to determine if the AP has been initialized successfully.

10. The method of claim 9, further comprising ending the multi-processor initialization when each AP has written initialization pass information to the third location in shared memory.

11. The method of claim 3, further comprising operating the BSP to store identification data for each AP.

12. The method of claim 11, wherein the BSP stores the identification data for the APs in one or more registers on an integrated circuit within which the BSP is integrated.

13. The method of claim 1, further comprising utilizing a plurality of microprocessors to provide the multiple APs.

14. An information handling system having multi-processor initialization for multiple application processors, comprising:

two or more application processors (APs) within an information handling system, at least one application processor (AP) configured to be a boot strap processor (BSP) for the information handling system;

a basic input output system (BIOS) coupled to the APs;

main memory coupled to the APs;

BSP code within the BIOS, the BSP code configured to cause the BSP to communicate with the other APs in order to initialize the APs prior to initialization of main memory; and

AP code within the BIOS, the AP code configured to cause each AP to communicate with the BSP for AP initialization.

15. The information handling system of claim 14, further comprising shared memory coupled to the BSP and to each other AP, the BSP code and AP code configured to cause the BSP and APs to utilize the shared memory to communicate for multi-processor initialization.

16. The information handling system of claim 15, wherein the shared memory is not part of the main memory.

17. The information handling system of claim 16, wherein the shared memory comprises a plurality of registers accessible to the BSP and the APs.

18. The information handling system of claim 14, further comprising a memory space coupled to the BSP and wherein the BSP code is configured to cause the BSP to store identification data for the APs in the memory space.

19. The information handling system of claim 14, further comprising a plurality of integrated circuit processors with each processor having a plurality of APs, one which is configured to be the BSP.

20. The information handling system of claim 19, wherein each integrated circuit processor has multiple processing cores.