COMPACTOR INDEPENDENT FAULT DIAGNOSIS
First Claim
1. A method, comprising:
- receiving a compressed failing response, the compressed failing response having been produced by a compactor of a circuit-under-test in response to a test pattern;
identifying one or more logic cones of the circuit-under-test in which a fault causing the compressed failing response might exist, the act of identifying being performed by applying a mathematical representation of the compactor to the compressed failing response;
determining a list of one or more fault candidates by simulating the test pattern being applied to the circuit-under-test in the presence of one or more simulated faults, the one or more simulated faults being located in at least one of the identified logic cones; and
storing the list of one or more fault candidates in one or more computer-readable media.
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Accused Products
Abstract
Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
74 Citations
21 Claims
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1. A method, comprising:
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receiving a compressed failing response, the compressed failing response having been produced by a compactor of a circuit-under-test in response to a test pattern;
identifying one or more logic cones of the circuit-under-test in which a fault causing the compressed failing response might exist, the act of identifying being performed by applying a mathematical representation of the compactor to the compressed failing response;
determining a list of one or more fault candidates by simulating the test pattern being applied to the circuit-under-test in the presence of one or more simulated faults, the one or more simulated faults being located in at least one of the identified logic cones; and
storing the list of one or more fault candidates in one or more computer-readable media. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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receiving a list of failing test responses from a test of an electronic circuit, the responses having been compressed by a compactor, and the electronic circuit comprising scan cells that receive test responses from a plurality of respective regions of the electronic circuit;
associating one or more of the respective regions of the electronic circuit with a selected failing test response using a description of relationships between one or more compactor inputs and one or more compactor outputs;
finding one or more fault candidates in the one or more associated regions of the electronic circuit using a model of the electronic circuit; and
storing a list of the one or more fault candidates in one or more computer-readable media. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system for testing a circuit-under-test, the system comprising:
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a processor;
one or more computer-readable media comprising instructions configured to cause the processor to perform a method, the method comprising;
receiving a failure log comprising one or more entries indicative of failing test responses captured in the circuit-under-test and compressed by a compactor;
for a selected entry of the failure log, identifying one or more candidate logic cones in the circuit using a transformation function indicative of which logic cones in the circuit-under-test at least partially contribute to respective failing test responses;
finding fault candidates in the one or more candidate logic cones using a representation of the circuit-under-test; and
storing a list of the fault candidates in one or more computer-readable media. - View Dependent Claims (18, 19, 20, 21)
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Specification