STRUCTURE COMPRISING 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, CIRCUIT STRUCTURE, AND INSTRUCTIONS FOR FABRICATION THEREOF

• US 20070283298A1
• Filed: 06/26/2007
• Published: 12/06/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bernstein, Kerry, Emma, Philip, Coteus, Paul
• Granted Patent: US 7,684,224 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A design structure comprising an integrated circuit architecture, circuit structure, and/or instructions for fabrication thereof. The circuit structure includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

Claims

1. A design structure instantiated in a machine readable medium for designing, manufacturing, or testing an integrated circuit architecture:

the design structure comprising;

a first array of first memory devices disposed on a first substrate layer, the first memory devices having a first power and performance specification;

a second array of second memory devices different from the first array disposed on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and

a plurality of logic devices disposed on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array.

2. The design structure of claim 1 further comprising a plurality of array sense-amp and memory array output drivers disposed on the third substrate layer and designed to interface with the first array and the second array.

3. The design structure of claim 1 wherein the first substrate layer, the second substrate layer and the third substrate layer are stacked.

4. The design structure of claim 1 wherein the first array of first memory devices comprises a series of devices selected as one from the group consisting of DRAM, SRAM, MRAM, flash memory, other volatile memory and other non-volatile memory devices.

5. The design structure of claim 4 wherein the second array of second memory devices comprises an other series of devices selected as an other from the group consisting of DRAM, SRAM, MRAM, flash memory, other volatile memory and other non-volatile memory devices.

6. The design structure of claim 1 wherein:

the third substrate layer further comprises a third array of third memory devices different from the second array of second memory devices and the first array of first memory devices, the third array of third memory devices having a third power and performance specification consistent with the plurality of logic devices.

7. The design structure of claim 1 further comprising a separate power supply for each of the first array, the second array and the plurality of logic devices.

8. The design structure of claim 1, wherein the design structure is a netlist.

9. The design structure of claim 1, wherein the design structure is embodied in a GDS medium.

10. A design structure instantiated in a machine readable medium for designing, manufacturing, or testing an integrated circuit structure:

the design structure comprising;

a first array of first memory devices located on a first substrate layer, the first memory devices having a first power and performance specification;

a second array of second memory devices different from the first array located on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and

a plurality of logic devices located on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array.

11. The design structure of claim 10 further comprising a plurality of array sense-amp and memory array output drivers located on the third substrate and interfaced with the first array and the second array.

12. The design structure of claim 10 wherein the first substrate layer, the second substrate layer and the third substrate layer comprise a stack.

13. The design structure of claim 10 wherein the first array of first memory devices comprises a series of devices selected as one from the group consisting of DRAM, SRAM, MRAM, flash memory, other volatile memory and other non-volatile memory devices.

14. The design structure of claim 13 wherein the second array of second memory devices comprises an other series of devices selected as another from the group consisting of DRAM, SRAM, MRAM, flash memory, other volatile memory and other non-volatile memory devices.

15. The design structure of claim 10 wherein the plurality of logic devices has a minimum channel width.

16. The design structure of claim 10 further comprising a bitline for coupling the first array, the second array and the plurality of logic devices.

17. The design structure of claim 10 further comprising a separate power supply for each of the first array, the second array and the plurality of logic devices.

18. The design structure of claim 10, wherein the design structure is a netlist.

19. The design structure of claim 10, wherein the design structure resides on a GDS medium.