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Enhanced OP3 algorithms for net cuts, net joins, and probe points for a digital design

  • US 20070283308A1
  • Filed: 08/11/2006
  • Published: 12/06/2007
  • Est. Priority Date: 06/05/2006
  • Status: Active Grant
First Claim
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1. A method of automating the determination of the optimal edit location on an integrated circuit for the purpose of making layout structural changes while maintaining logic design integrity, comprising the method steps of:

  • a. providing a database for said integrated circuit, said database including functional unit placement and connectivity data including conducting net data, and building blocks of different functional units and features in layout form, said database containing said functional unit placement and connectivity data, and said building block data of different functional units and features being in polygon form;

    b. providing layer-by-layer layout information for said integrated circuit;

    c. providing an interface with said database to acquire all feature polygons on a given integrated circuit design;

    d. applying user defined constraints and limitations to optimize edit location searches;

    e. using enhanced algorithms to find, from said database and said layout information, the optimal at least one edit location under said user defined constraints; and

    f. reporting said optimal at least one edit location to said user.

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