Multi-threaded processor with deferred thread output control

• US 20070283356A1
• Filed: 05/31/2006
• Published: 12/06/2007
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Du, Yun, Jiao, Guofang, Yu, Chun
• Granted Patent: US 8,869,147 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.

Claims

1. A multi-threaded processor comprising:

a thread scheduler to track a sequence in which a plurality of threads are received from an application;

an internal memory buffer to temporarily store the plurality of received threads; and

a processing unit coupled to the thread scheduler and internal memory buffer, the processing unit configured to

process the plurality of threads to obtain a plurality of corresponding results, and

store the plurality of results in the internal memory buffer,

wherein the thread scheduler causes the plurality of stored results to be outputted from the internal memory buffer according to the sequence in which the corresponding threads were received from the application.

2. The multi-threaded processor of 1 wherein the plurality of threads are processed by the processing unit according to the order defined by flow control instructions associated with the plurality of threads.

3. The multi-threaded processor of 2 wherein the flow control instructions cause the plurality of threads to be processed in a different sequence than they were received.

4. The multi-threaded processor of 1 wherein the memory buffer further includes

a plurality of input registers to store the plurality of received threads prior to processing and a plurality of output registers to store the plurality of results prior to being outputted.

5. The multi-threaded processor of 4 wherein processing unit is further configured to

retrieve a thread from one of the plurality of input registers in the memory buffer.

6. The multi-threaded processor of 1 further comprising:

an input interface coupled to the thread scheduler to receive the plurality of threads; and

an output interface coupled to the memory buffer from which the plurality of stored results are outputted.

7. The multi-threaded processor of 1 further comprising:

a load controller coupled to the thread scheduler and configured to store the plurality of threads in a plurality of input registers in the internal memory buffer under the direction of the thread scheduler.

8. The multi-threaded processor of 7 wherein the load controller outputs the results from the internal memory buffer under the direction of the thread scheduler.

9. The multi-threaded processor of 1 wherein the received threads include pixel data.

10. A multi-threaded processor comprising:

means for tracking a sequence in which a plurality of threads are received;

means for processing the plurality of threads to obtain a plurality of corresponding results;

means for storing the plurality of results in an internal memory buffer; and

means for causing the plurality of stored results to be outputted from the internal memory buffer according to the sequence in which the corresponding threads were received.

11. The multi-threaded processor of 10 wherein the plurality of threads are processed according to the order defined by flow control instructions associated with the plurality of threads.

12. The multi-threaded processor of 10 further comprising:

means for storing the plurality of threads in the internal memory buffer prior to processing.

13. A method for reordering the sequence of a plurality thread results within a multi-threaded processor comprising:

tracking a sequence in which a plurality of threads are received;

processing the plurality of threads to obtain a plurality of corresponding results;

storing the plurality of results in an internal memory buffer; and

sending out the plurality of stored results from the memory buffer according to the sequence in which the corresponding threads were received.

14. The method of 13 wherein the plurality of threads are processed according to the order defined by flow control instructions associated with the plurality of threads.

15. The method of 13 further comprising:

receiving a plurality of threads for a particular process at a multi-threaded processor; and

storing the plurality of threads in the memory buffer prior to processing.

16. A graphics processor comprising:

a multi-threaded processor configured to

track a sequence in which a plurality of threads including pixel data are received from a first application;

store the plurality of received threads in an internal memory buffer; and

process the plurality of threads according to an order defined by flow control instructions associated with the plurality of threads to obtain a plurality of corresponding results;

store the plurality of results in the internal memory buffer;

output the plurality of results to the first application from the internal memory buffer according to the sequence in which the corresponding threads were received from the application.

17. The graphics processor of 16 wherein the flow control instructions cause the plurality of threads to be processed in a different sequence than they were received

18. A method operational on a multi-thread processor compiler, comprising:

receiving a plurality of instructions to be compiled for operation on a multi-threaded processor;

identifying output instructions in the plurality of instructions that direct output results to an external register; and

converting the identified output instructions to direct the output results to an internal register.

19. The method of 18 further comprising:

compiling the plurality of instructions for processing by the multi-threaded processor.

20. The method of 18 further wherein the multi-threaded processor supports flow control instructions cause threads to be processed in a different order than they are received.

21. A machine-readable medium having one or more instructions for compiling instructions for a multi-threaded processor, which when executed by a processor causes the processor to:

receive a plurality of instructions to be compiled for operation on a multi-threaded processor;

identify output instructions in the plurality of instructions that direct output results to an external register; and

convert the identified output instructions to direct the output results to an internal register.

22. The machine-readable medium of 21 further having one or more instructions which when executed by a processor causes the processor to:

compile the plurality of instructions for processing by the multi-threaded processor with flow control support.