Managing Bad Blocks In Flash Memory For Electronic Data Flash Card

• US 20070283428A1
• Filed: 09/07/2006
• Published: 12/06/2007
• Est. Priority Date: 01/06/2000
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, I-Kang, Lee, Edward W., Shen, Ming-Shiang
• Granted Patent: US 7,690,031 B2
• Time in Patent Office: Days
• US Class Current: 726/9
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/07354 by biometrically sensitive means, e.g. fingerprint sensitive fingerprint sensors in general G06V40/12; biometrically activated access control G07C9/25
• CPC Class Codes: G06V 40/1365 Matching; Classification
• CPC Class Codes: G07C 9/257 electronically G07C9/26 takes precedence
• CPC Class Codes: H03M 13/153 using the Berlekamp-Massey algorithm
• CPC Class Codes: H03M 13/1535 using the Euclid algorithm
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
• CPC Class Codes: H03M 13/6561 Parallelized implementations

Abstract

An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

Claims

1. An electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, said electronic data flash card comprising:

a card body;

one or more flash memory devices mounted on the card body, the flash memory device including a plurality of non volatile memory cells for storing a data file;

an input/output interface circuit mounted on the card body for establishing communication with the host computer; and

a flash memory controller mounted on the card body and electrically connected to said flash memory device and said input/output interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller in accordance with a flash detection algorithm code,

(b) arbitration means for identifying non-functional memory cells of the flash memory device, and for assigning physical block addresses to an associated logical block address, where each said physical block address corresponds to an associated plurality of memory cells of the flash memory device;

(c) means for selectively operating in one of;

a programming mode in which said flash memory controller activates said input/output interface circuit to receive the data file from the host computer, and to store the data file in a first physical file address of said flash memory device that is assigned by said arbitration means to a first logical block address, said programming mode being initiated in response to an associated write command issued from the host computer to the flash memory controller;

a data retrieving mode in which said flash memory controller receives a read command issued from host computer including the first logical block address, and activates said input/output interface circuit to transmit the data file read from the first physical address to the host computer; and

a data resetting mode in which the data file is erased from the flash memory device.

2. The electronic data flash card according to claim 1, wherein the one or more flash memory devices include a first flash memory device and a second flash memory device.

3. The electronic data flash card according to claim 2, wherein the first flash memory device includes a first plurality of memory cells and the second flash memory device includes a second plurality of memory cells, and wherein the first plurality is greater than or equal to the second plurality.

4. The electronic data flash card according to claim 2, wherein said arbitration means includes means for performing at least one of a programming operation, a data retrieving operation, and a data resetting operation in the first flash memory device while simultaneously performing at least one of a programming operation, a data retrieving operation, and a data resetting operation in the second flash memory device.

5. The electronic data flash card according to claim 1, wherein said arbitration means includes means for searching the flash memory device for functional memory cells, and for reassigning the first logical block address associated with one or more non-functional memory cells to a second physical block address associated with the functional memory cells.

6. The electronic data flash card according to claim 1, wherein said flash memory device includes an internal buffer, and wherein the flash memory controller includes means for temporarily storing said data file in said internal buffer prior to storing said data in the memory cells associated with said first physical block address.

7. The electronic data flash card according to claim 1, wherein said arbitration means further comprises means for identifying non-functional memory cells previously assigned to said first logical block address, for identifying functional, unassigned memory cells associated with a second physical block address, and for reassigning said first logical block address to the second physical block address.

8. The electronic data flash card according to claim 1, wherein said arbitration means further comprises means for identifying an updated data file assigned to the first logical block address, for reassigning the first logical block address to a second physical block address, and for storing the updated data file in the memory cells associated with the second physical block address.

9. The electronic data flash card according to claim 8, wherein said arbitration means further comprises means for erasing obsolete data from the memory cells associated with said first physical block address after storing the updated data file in the memory cells associated with the second physical block address, and for reassigning the first physical block address to a second logical block address.

10. The electronic data flash card according to claim 1, wherein said arbitration means further comprises means for comparing a first erase count associated with the memory cells of the first physical block address with a second erase count associated with the memory cells of a second physical block address, and transferring the data file from the memory cells of the first physical block address to the memory cells of a second physical block address when the first erase count is greater than the second erase count.

11. The electronic data flash card according to claim 10, wherein said flash memory device includes an internal buffer, and wherein the flash memory controller includes means for temporarily storing said data file in said internal buffer prior to storing said data in the memory cells associated with said second physical block address.

12. The electronic data flash card according to claim 2, wherein the flash memory controller includes means for supporting at least one of dual-channel parallel access and interleave access to the first flash memory device and the second flash memory device.

13. The electronic data flash card according to claim 1, wherein the input/output interface circuit comprises a Universal Serial Bus (USB) interface circuit, and wherein the USB interface circuit includes means for transmitting said data using a Bulk Only Transport (BOT) protocol.

14. The electronic data flash card according to claim 1, wherein the input/output interface circuit comprises one of a Secure Digital (SD) interface circuit, a Multi-Media Card (MMC) interface circuit, a Compact Flash (CF) interface circuit, a Memory Stick (MS) interface circuit, a PCI-Express interface circuit, a Integrated Drive Electronics (IDE) interface circuit, and a Serial Advanced Technology Attachment (SATA) interface circuit.