Semiconductor device having vertical channel transistor

• US 20070284623A1
• Filed: 05/24/2007
• Published: 12/13/2007
• Est. Priority Date: 05/24/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sang-Jin, Yeo, Gi-sung, Park, Joon-soo, Cho, Han-ku, Woo, Sang-gyun, Hong, Min-jong
• Application Number:
  US11/802,647
• Publication Number:
  US 20070284623A1
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

Claims

1. A semiconductor device, comprising:

a substrate; and

a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein;

the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction,

the even columns include active pillars spaced at the first pitch,

active pillars in the odd columns are spaced apart from active pillars in the even columns by a third pitch, the third pitch being determined in the row direction, and

active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

2. The semiconductor device as claimed in claim 1, further comprising at least one word line extending in the row direction, the word line electrically connecting active pillars in an odd row with active pillars in an adjacent even row.

3. The semiconductor device as claimed in claim 2, wherein the word line partially surrounds the channel portions of the active pillars to which it is connected.

4. The semiconductor device as claimed in claim 2, wherein adjacent word lines are spaced at the first pitch.

5. The semiconductor device as claimed in claim 1, further comprising at least one bit line within the substrate, the bit line extending in the column direction.

6. The semiconductor device as claimed in claim 5, wherein the bit line includes an impurity region within the substrate, the impurity region extending in the column direction.

7. The semiconductor device as claimed in claim 1, further comprising at least one bit line within the substrate and extending in the row direction, the bit line electrically connecting active pillars in an odd row with active pillars in an adjacent even row.

8. The semiconductor device as claimed in claim 7, wherein adjacent bit lines are spaced at the first pitch.

9. The semiconductor device as claimed in claim 7, further comprising at least one word line extending in the column direction and electrically connected to a plurality of active pillars, the word line partially surrounding the channel portions of the active pillars to which it is connected.

10. The semiconductor device as claimed in claim 9, wherein adjacent word lines are spaced at the third pitch.

11. The semiconductor device as claimed in claim 1, further comprising storage node electrodes disposed on the active pillars and respectively connected to the active pillars.

12. The semiconductor device as claimed in claim 11, wherein the storage node electrodes are arranged in the same fashion as the arrangement of the active pillars.

13. The semiconductor device as claimed in claim 11, wherein storage node electrodes in the even columns have centers that are substantially aligned with centers of storage node electrodes in the odd columns,

the columns include storage node electrodes spaced at the first pitch, and

the rows include storage node electrodes spaced at the third pitch.

14. The semiconductor device as claimed in claim 1, wherein the second pitch is about ½

of the first pitch.

15. The semiconductor device as claimed in claim 1, wherein the first pitch is about ⅔

to about 3/2 of the third pitch.

16. A semiconductor device, comprising:

a substrate;

a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein;

the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction,

the even columns include active pillars spaced at the first pitch,

the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction,

the odd rows include active pillars spaced at the third pitch, and

active pillars in the even columns have centers that are substantially aligned with centers of active pillars in the odd columns; and

storage node electrodes disposed on and electrically connected to respective active pillars, wherein;

storage node electrodes in the odd columns are spaced at the first pitch,

storage node electrodes in the even columns are spaced at the first pitch, and

storage node electrodes in the even columns are offset by a second pitch from storage node electrodes in the odd columns.

17. The semiconductor device as claimed in claim 16, further comprising word lines extending along rows of the active pillars, and bit lines extending along columns of the active pillars.

18. The semiconductor device as claimed in claim 16, further comprising word lines extending along columns of the active pillars, and bit lines extending along rows of the active pillars.

19. The semiconductor device as claimed in claim 16, wherein the second pitch is about ½

of the first pitch.

20. The semiconductor device as claimed in claim 16, wherein the first pitch is about ⅔

to about 3/2 of the third pitch.