Non-volatile memory device and method of manufacturing the same

• US 20070284648A1
• Filed: 03/19/2007
• Published: 12/13/2007
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jung-Hoon, Park, Yoon-dong, Kim, Won-joo, Koo, June-mo, Kim, Suk-pil, Hyun, Jae-woong
• Granted Patent: US 7,622,761 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

Claims

1. A non-volatile memory device comprising:

a semiconductor substrate having a body, and a pair of fins projecting from the body and spaced apart opposite each other; and

a bridge insulating layer non-electrically connecting upper portions of the pair of fins to define a void between the pair of fins.

2. The non-volatile memory device of claim 1, wherein outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void.

3. The non-volatile memory device of claim 2, further comprising:

at least one control gate electrode covering at least a portion of the outer surfaces of the pair of fins, extending over the bridge insulating layer, and isolated from the semiconductor substrate;

at least one pair of gate insulating layers between the at least one control gate electrode and the pair of fins; and

at least one pair of storage nodes between the at least one pair of gate insulating layers and the at least one control gate electrode.

4. The non-volatile memory device of claim 3, wherein the at least one control gate electrode includes a plurality of control gate electrodes, the at least one pair of gate insulating layers includes a plurality of pairs of gate insulating layers and the at least one pair of storage nodes includes a plurality of pairs of storage nodes.

5. The non-volatile memory device of claim 1, wherein the bridge insulating layer is on top of the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

6. The non-volatile memory device of claim 1, wherein the bridge insulating layer extends to contact the upper portions of the inner surfaces of the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

7. The non-volatile memory device of claim 3, further comprising:

a device isolation layer adjacent to lower portions of the outer surfaces of the pair of fins and between the at least one control gate electrode and the body.

8. The non-volatile memory device of claim 3, wherein the at least one pair of gate insulating layers are formed on the outer surfaces of the pair of fins.

9. The non-volatile memory device of claim 8, wherein the at least one pair of gate insulating layers are further formed on the top portions of the pair of fins.

10. The non-volatile memory device of claim 3, further comprising:

at least one source region formed in the pair of fins on one side of the at least one control gate electrode and at least one drain region formed in the pair of fins on the other side of the at least one control gate electrode.

11. The non-volatile memory device of claim 1, wherein the semiconductor substrate is formed by etching a bulk semiconductor wafer.

12. The non-volatile memory device of claim 8, wherein the at least one pair of gate insulating layers are further formed on the upper ends of the pair of fins.

13. The non-volatile memory device of claim 10, wherein the bridge insulating layer is filled in upper end portions between the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

14. The non-volatile memory device of claim 1, wherein the void has a lower dielectric constant than that of an insulating layer.

15. The non-volatile memory device of claim 1, wherein the pair of fins are not completely floating from the body.

16. A method of manufacturing a non-volatile memory device comprising:

etching a semiconductor substrate to define a body and a pair of fins each projecting from the body; and

forming a bridge insulating layer connecting portions of the pair of fins to define a void between the pair of fins.

17. The method of claim 16, further comprising:

forming gate insulating layers partially covering outer surfaces of the pair of fins which do not face the void;

forming storage node layers covering the gate insulating layers; and

forming a control gate electrode covering the storage node layers, and extending over the bridge insulating layer.

18. The method of claim 16, wherein the bridge insulating layer is further formed on the pair of fins and the body within the void, and the void is defined within the bridge insulating layer.

19. The method of claim 16, wherein the bridge insulating layer is formed by plasma enhanced chemical vapor deposition (PECVD).

20. The method of claim 19, wherein the bridge insulating layer is filled in the upper end portion between the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

21. The method of claim 19, wherein the bridge insulating layer extends over the upper end portions of the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

22. The method of claim 16, wherein defining the body and the pair of fins comprises:

forming a pair of first trenches in the semiconductor substrate;

forming a device isolating layer filled in the first trenches and projecting from the semiconductor substrate;

forming spacer insulating layers along the projecting sidewalls of the device isolating layer; and

etching the semiconductor substrate exposed between the spacer insulating layers to define the pair of fins projecting from the body.

23. The method of claim 22, wherein the spacer insulating layers include a nitride layer or an oxide layer and a nitride layer.

24. The method of claim 22, after defining the pair of fins, further comprising:

forming a capping layer that connects the spacer insulating layers and defines the void between the pair of fins,

wherein the bridge insulating layer comprises the spacer insulating layers and the capping layer.

25. The method of claim 24, wherein the capping layer includes a silicon nitride layer.

26. The method of claim 24, wherein the void is defined by the capping layer without the spacer insulating layers.

27. The method of claim 24, after forming the capping layer, further comprising:

etching the device isolating layer to a predetermined depth to expose portions of outer surfaces of the pair of fins.