Methods and apparatus for thermal management in a multi-layer embedded chip structure

• US 20070284711A1
• Filed: 06/09/2006
• Published: 12/13/2007
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Lee, Tien Yu T., Chiriac, Victor A., Amrine, Craig S., Leal, George R., Wenzel, Robert J., Keser, Lizabeth Ann
• Granted Patent: US 7,405,102 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0373 Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool providing micro- or nanometer scale roughness on a metal surface H05K2203/0307
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/10416 : Metallic blocks or heatsinks completely inserted in a PCB metallic supports H05K3/0061
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4641 : having integrally laminated metal sheets or special power cores

Abstract

A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Claims

1. A multi-layer package structure comprising:

a first build-up layer structure configured to connect to a heat-generating module;

a second build-up layer structure configured to connect to a substrate;

a middle layer provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component and a heat spreader;

a first set of thermal vias extending through the first build-up layer structure to the heat spreader, and a second set of thermal vias extending through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

2. The structure of claim 1, wherein the heat-generating module is a power amplifier module including at least one power transistor device.

3. The structure of claim 2, wherein the first set of thermal vias has a via pattern substantially corresponding to a position of the at least one power transistor device.

4. The structure of claim 1, wherein the first set of thermal vias has a via pattern substantially corresponding to a footprint of the heat-generating module.

5. The structure of claim 1, wherein the heat spreader includes a plurality of slots opening to at least one of the first and second build-up layers.

6. The structure of claim 1, wherein the heat spreader includes at least one through-hole extending from the first build-up layer to the second build-up layer.

7. The structure of claim 1, wherein the heat spreader comprises a material selected from the group consisting of metal and ceramic.

8. The stricture of claim 1, wherein the thermal vias are copper-filled.

9. A method for improving heat transfer in an electronic assembly, the method including:

providing a heat-generating module;

providing a multi-layer embedded chip structure having a top surface and a bottom surface, wherein a predetermined area on the top surface is configured to connect to the heat-generating module, and the bottom surface is configured to connect to a substrate;

the multi-layer embedded chip structure comprising a heat spreader and a semiconductor device, wherein the heat spreader is substantially coincident with the predetermined location and has a plurality of thermal vias thermally coupled to the heat spreader and extending to the top and bottom surfaces of the multi-layer embedded chip structure;

connecting the heat-generating module to the predetermined location on the top surface of the multi-layer embedded chip structure; and

connecting the bottom surface of the multi-layer embedded chip structure to a substrate.

10. The method of claim 9, wherein providing the heat generating module includes providing a power amplifier module comprising at least one power transistor device.

11. A method for fabricating a multi-layer embedded chip structure, the method comprising:

forming a panel layer, the panel layer comprising a heat spreader, a semiconductor die, and an encapsulant material provided between the heat spreader and semiconductor die; and

forming, on the panel layer, a bottom build-up layer structure configured to connect to a heat-generating module, the bottom build-up layer including a plurality of thermal vias coupled to the panel layer; and

forming a top build-up layer structure on the panel layer, the top build-up layer structure including a plurality of thermal vias coupled to the heat spreader.

12. The method of claim 11, wherein forming the panel layer includes forming a metallic heat spreader.

13. The method of claim 11, wherein the semiconductor die is a memory component.

14. The method of claim 11, wherein the plurality of thermal vias has a via pattern substantially corresponding to a predetermined position on the top build-up layer.

15. The method of claim 11, wherein the heat spreader includes a plurality of slots opening to at least one of the top and bottom build-up layers.

16. The method of claim 11, wherein forming the panel layer includes:

placing the semiconductor die and the heat spreader on a surface;

depositing the encapsulant material on the semiconductor die, the heat spreader, and the surface; and

grinding the encapsulant material to expose a portion of the semiconductor die.

17. The method of claim 11, wherein the heat spreader comprises a material selected from the group consisting of metal and ceramic.

18. The method of claim 11, wherein forming the thermal vias includes forming copper-filled vias.

19. The method of claim 11, wherein the step of forming the top build-up layer includes forming a plurality of dielectric layers.

20. The method of claim 11, wherein forming the top build-up layer includes forming a plurality of electrical vias coupled to the semiconductor die.