Power MOSFET contact metallization

• US 20070284754A1
• Filed: 05/02/2007
• Published: 12/13/2007
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Terrill, Kyle, Chen, Kuo-In, Wong, Ronald, Qi, Jason
• Granted Patent: US 8,471,390 B2
• Time in Patent Office: Days
• US Class Current: 257/771
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Claims

1. A method of fabricating a structure comprising a semiconductor device, said method comprising:

depositing a first metallized layer over an uneven surface comprising an insulator and a contact area adjacent to said insulator; and

etching said first metallized layer to form an electrical contact in said contact area, wherein a surface of said insulator and a surface of said electrical contact form a substantially level surface.

2. The method of claim 1 wherein said first metallized layer comprises tungsten.

3. The method of claim 1 wherein said first metallized layer is deposited using chemical vapor deposition.

4. The method of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

5. The method of claim 1 further comprising depositing a barrier layer over said uneven surface prior to depositing said first metallized layer.

6. The method of claim 1 further comprising depositing a barrier layer over said substantially level surface subsequent to said etching.

7. The method of claim 1 further comprising:

depositing a second metallized layer subsequent to said etching; and

etching said second metallized layer to form an electrical connector coupled to said electrical contact.

8. The method of claim 7 wherein said second metallized layer comprises aluminum.

9. A structure comprising:

a semiconductor device formed in a substrate;

an insulator coupled to said semiconductor device; and

an electrical contact coupled to said insulator, wherein a surface of said insulator and a surface of said electrical contact form a substantially even surface.

10. The structure of claim 9 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

11. The structure of claim 9 wherein said electrical contact comprises tungsten.

12. The structure of claim 9 further comprising an electrical connector coupled to said electrical contact.

13. The structure of claim 9 wherein said electrical connector comprises aluminum.

14. The structure of claim 9 wherein said electrical contact has a dimension in the range of approximately 0.35-0.50 microns.

15. A structure comprising:

a semiconductor device formed in a substrate;

an insulator coupled to said semiconductor device;

an electrical contact electrically coupled to said semiconductor device, wherein said electrical contact comprises tungsten; and

an electrical connector coupled to said electrical contact, wherein said electrical connector comprises aluminum.

16. The structure of claim 15 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

17. The structure of claim 15 wherein said electrical contact has a dimension in the range of approximately 0.35-0.50 microns.

18. The structure of claim 15 wherein a surface of said insulator and a surface of said electrical contact form a substantially even surface.

19. The structure of claim 15 wherein said electrical contact is a planar contact that does not extend into said substrate.

20. The structure of claim 15 wherein said electrical contact is a trench contact that extends into said substrate.