BITLINE EXCLUSION IN VERIFICATION OPERATION
First Claim
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1. A method of performing operations on a bitline in a memory device, comprising:
- setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and
disabling the bitline for verification operation, wherein disabling the bitline for verification operation comprises pulling a verification node to ground.
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Accused Products
Abstract
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
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Citations
19 Claims
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1. A method of performing operations on a bitline in a memory device, comprising:
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setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and
disabling the bitline for verification operation, wherein disabling the bitline for verification operation comprises pulling a verification node to ground.
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2. A memory device, comprising:
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an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a program verify circuit comprising;
first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.
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3. A memory device, comprising:
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an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.
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4. A memory device, comprising:
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an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a bitline disable circuit comprising;
a bitline disable latch having an input and an output;
a program latch having an input and an output; and
a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;
a program verify circuit comprising;
second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed. - View Dependent Claims (5, 6, 7)
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8. A non-volatile memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a program verify circuit comprising;
first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground. - View Dependent Claims (9, 10)
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11. A non-volatile memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.
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12. A non-volatile memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a bitline disable circuit comprising;
a bitline disable latch having an input and an output;
a program latch having an input and an output; and
a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;
a program verify circuit comprising;
second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.
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13. A processing system, comprising:
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a processor; and
a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;
an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a program verify circuit comprising;
first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.
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14. A processing system, comprising:
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a processor; and
a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;
an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed. - View Dependent Claims (15)
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16. A processing system, comprising:
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a processor; and
a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;
an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;
a bitline disable circuit comprising;
a bitline disable latch having an input and an output;
a program latch having an input and an output; and
a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;
a program verify circuit comprising;
second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.
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17. A flash memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a program verify circuit comprising;
first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.
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18. A flash memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.
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19. A flash memory device, comprising:
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an array of floating gate memory cells;
control circuitry to read, write and erase the floating gate memory cells; and
address circuitry to latch address signals provided on address input connections; and
a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;
a bitline disable circuit comprising;
a bitline disable latch having an input and an output;
a program latch having an input and an output; and
a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;
a program verify circuit comprising;
second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and
a read/verify sense circuit comprising;
a sense precharge transistor source to drain connected between a supply voltage and a sense node;
a bitline sense transistor source to drain connected between the sense node and a bitline; and
a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.
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Specification