Radio Watch

• US 20070286028A1
• Filed: 06/08/2006
• Published: 12/13/2007
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Meltzer, David, Blum, Gregory
• Granted Patent: US 7,719,928 B2
• Time in Patent Office: Days
• US Class Current: 368/47
• CPC Class Codes: G04R 20/10 Tuning or receiving; Circuits therefor

Abstract

Apparatuses, circuits, and methods for receiving at least one radio signal in a radio controlled timing apparatus using a single timing source. The present invention advantageously eliminates the need to provide an additional timing source to receive at least one radio signal, and therefore reduces the material cost and eliminates many engineering challenges.

Claims

1. A radio controlled timing apparatus comprising:

a) a radio receiver configured to (i) receive a local carrier signal derived from a reference timing signal and at least one modulated time code signal and (ii) generate a time code signal from said local carrier signal and said at least one modulated time code signal;

b) a decoder configured to (i) receive said time code signal and (ii) generate a time setting and/or correction signal therefrom; and

c) a timing mechanism configured to receive (i) a real-time signal derived from said reference timing signal and (ii) said time setting and/or correction signal.

2. The apparatus of claim 1, further comprising a real-time signal generator configured to (i) receive said reference timing signal and (ii) generate said real-time signal therefrom.

3. The apparatus of claim 2, wherein said real-time signal generator further comprises at least one divider configured to generate said real-time signal.

4. The apparatus of claim 1, further comprising a frequency synthesizer configured to (i) receive said reference timing signal and (ii) generate said local carrier signal therefrom.

5. The apparatus of claim 4, wherein said frequency synthesizer further comprises:

a) a phase locked loop; and

b) at least one divider.

6. The apparatus of claim 5, wherein said divider has a ratio determined by a frequency control signal.

7. The apparatus of claim 1, further comprising at least one antenna and/or at least one amplifier configured to receive and/or amplify said at least one modulated time code signal.

8. The apparatus of claim 1, wherein said modulated time code signal has a frequency of from about 40 kHz to about 77.5 kHz.

9. The apparatus of claim 1, wherein said time code signal is encoded with at least the current time.

10. The apparatus of claim 1, wherein said decoder is contained within a microprocessor, a logic array element, or an application specific integrated circuit.

11. The apparatus of claim 1, wherein said timing mechanism is configured to synchronize said real-time signal and said time setting and/or correction signal.

12. A circuit for a radio controlled timing apparatus circuit comprising:

a) a frequency synthesizer configured to (i) receive a reference timing signal and a selectable frequency control signal and (ii) generate a local carrier signal from said reference timing signal and said selectable frequency control signal; and

b) a radio receiver configured to (i) receive said local carrier signal and said at least one modulated time code signal and (ii) generate a time code signal from said local carrier signal said at least one modulated time code signal.

13. The circuit of claim 12, further comprising a reference timing signal source.

14. The circuit of claim 12, further comprising a decoder configured to (i) receive said time code signal and (ii) generate a time setting and/or correction signal therefrom.

15. The circuit of claim 12, further comprising at least one amplifier configured to amplify said at least one modulated time code signal.

16. The circuit of claim 12, further comprising a real-time signal generator configured to (i) receive said reference timing signal and (ii) generate a real-time signal therefrom.

17. The circuit of claim 16, wherein said real-time signal generator further comprises at least one divider configured to generate said real-time signal.

18. The circuit of claim 12, further comprising at least one antenna and/or at least one amplifier configured to receive and/or amplify said at least one modulated time code signal.

19. The circuit of claim 12, wherein said frequency synthesizer further comprises:

a) a phase locked loop; and

b) at least one divider.

20. The circuit of claim 12, wherein said modulated time code signal has a frequency of from about 40 kHz to about 100 kHz.