METHOD AND SYSTEM FOR PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY

• US 20070286078A1
• Filed: 08/22/2007
• Published: 12/13/2007
• Est. Priority Date: 11/28/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tremaine, Robert, Maule, Warren, Gower, Kevin, Coteus, Paul
• Granted Patent: US 8,145,868 B2
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A method and system for providing frame start indication in a memory system having indeterminate read data latency. The method includes receiving a data transfer and determining if the data transfer includes a frame start indicator. The method also includes capturing the data transfer and “n” subsequent data transfers in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers comprise a data frame.

Claims

1. A method for providing frame start indication in a memory system having indeterminate read data latency, the method comprising:

receiving a data transfer;

determining if the data transfer includes a frame start indicator;

capturing the data transfer and “

n”

subsequent data transfers in response to determining that the data transfer includes a frame start indicator, the data transfer and the “

n”

subsequent data transfers comprising a data frame.

2. The method of claim 1 wherein the determining includes checking a bit position in the data transfer for a frame start indicator value.

3. The method of claim 1 wherein the determining includes checking a plurality of bit positions in the data transfer for a frame start indicator value.

4. The method of claim 1 wherein the determining includes checking a bit position in the data transfer and at least one bit position in one or more of the subsequent data transfers for frame start indicator values and capturing the data transfer and “

n”

subsequent data transfers in response to determining that the data transfer and the one or more subsequent data transfers include the frame start indicator values.

5. The method of claim 1 wherein a parity bit in the data transfer is utilized to validate the determining that the data transfer includes a frame start indicator.

6. The method of claim 1 wherein the data frame includes a read data identification tag for use by a memory controller in the memory system in associating the data frame with its corresponding read instruction.

7. A hub device for providing frame start indication in a memory system having indeterminate read data latency, the hub device comprising:

a mechanism for receiving data transfers via an upstream or downstream channel and for determining if a data transfer includes a frame start indicator;

a mechanism for capturing the data transfer and “

n”

subsequent data transfers in response to determining that the data transfer includes the frame start indicator, the data transfer and the “

n”

subsequent data transfers comprising a data frame; and

a mechanism for transmitting the data frames via an upstream or downstream channel, each transmitted data frame including a frame start indicator.

8. The hub device of claim 7 wherein at least one of the transmitted data frames is created at the hub device and the hub device includes a mechanism for adding the frame start indicator to the transmitted data frame.

9. The hub device of claim 7 wherein the data frame includes a read data identification tag for use by a memory controller in associating the data frame with its corresponding read instruction.

10. The hub device of claim 7 wherein the determining includes checking a bit position in the data transfer for a frame start indicator value.

11. The hub device of claim 7 wherein the determining includes checking a plurality of bit positions in the data transfer for a frame start indicator value.

12. The hub device of claim 7 wherein the determining includes checking a bit position in the data transfer and at least one bit position in one or more of the subsequent data transfers for frame start indicator values and capturing the data transfer and “

n”

subsequent data transfers in response to determining that the data transfer and the one or more subsequent data transfers include the frame start indicator values.

13. The hub device of claim 7 wherein a parity bit in the data transfer is utilized to validate the determining that the data transfer includes a frame start indicator.

14. A memory controller in a memory system having indeterminate read data latency, the memory controller comprising:

a mechanism for receiving data transfers via an upstream channel and for determining if a data transfer includes a frame start indicator;

a mechanism for capturing the data transfer and “

n”

subsequent data transfers in response to determining that the data transfer includes the frame start indicator, the data transfer and the “

n”

subsequent data transfers comprising a data frame, the data frame including a read data identification tag; and

a mechanism for associating the data frame with its corresponding read instruction issued by the memory controller using the read data identification tag.

15. The memory controller of claim 14 wherein the data frame is a requested data frame.

16. The memory controller of claim 14 wherein the data frame is an un-requested data frame.

17. The memory controller of claim 14 further comprising:

a mechanism for generating read data instructions and for transmitting the read data instructions to one or more downstream devices via a downstream channel.

18. A memory system having indeterminate read data latency, the memory system comprising:

a memory controller for receiving data transfers via an upstream channel and for determining if all or a subset of the data transfers comprise a data frame by detecting a frame start indicator, wherein the data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller; and

one or more hub devices in communication with the memory controller in a cascade interconnect manner via an upstream channel and a downstream channel, each hub device receiving the data transfers via the upstream channel or the downstream channel and determining if all or a subset of the data transfers comprise a data frame by detecting the frame start indicator.

19. The memory system of claim 18 wherein one or more of the hub devices include memory devices and a mechanism for processing the read instruction when it is directed to one of the memory devices, the processing including creating a data frame having the frame start indicator.

20. The memory system of claim 18 wherein the memory controller further generates read data instructions and transmits the read data instructions to one or more of the hub devices via the downstream channel.