METHODS OF FORMING SOLDER CONNECTIONS AND STRUCTURE THEREOF

• US 20070287278A1
• Filed: 06/08/2006
• Published: 12/13/2007
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Daubenspeck, Timothy H., Gambino, Jeffrey P., Muzzy, Christopher D., Sauter, Wolfgang
• Granted Patent: US 7,682,961 B2
• Time in Patent Office: Days
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/03914 the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11912 : the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13006 : Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In a first aspect, a method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

Claims

1. A method comprising:

depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure;

patterning at least one opening, in a resist, to the first metal containing layer, the opening being in substantial alignment with the trench structure;

forming at least a pad metal containing layer or bilayer within the at least one opening;

stripping the resist and etching the first metal layer underlying the resist; and

flowing solder material within the trench structure and on the pad metal containing layer.

2. The method according to claim 1, further comprising forming a passivation layer under the first metal layer and forming an opening in the passivation layer to form the trench structure.

3. The method of claim 2, wherein the passivation layer comprises at least one of silicon nitride, silicon oxide and polyimide.

4. The method according to claim 1, wherein the first metal containing layer comprises at least one of the class of refractory metals or their alloys including titanium, tungsten, titanium-tungsten alloy.

5. The method according to claim 1, wherein the solder material is provided after the resist stripping.

6. The method according to claim 1, wherein the first metal containing layer is deposited by physical vapor deposition.

7. The method according to claim 1, wherein the pad metal containing layer comprises copper or copper with a diffusion barrier metal including nickel or alloys of nickel.

8. The method according to claim 1, wherein the pad metal containing layer or bilayer is deposited by electroplating.

9. The method according to claim 1, wherein the pad metal containing layer is between about 2 to about 3 μ

m thick.

10. The method according to claim 1, wherein a longitudinal dimension of the pad metal layer is controlled by the resist pattern.

11. The method according to claim 1, wherein the solder material is placed within the trench prior to the etching of the resist.

12. The method according to claim 11, wherein the solder material is used as a mask to etch the first metal containing layer after the etching of the resist.

13. The method according to claim 1, wherein the solder material comprises lead free tin containing material or lead reduced tin containing material.

14. The method according to claim 1, wherein the etching comprises reactive ion etching.

15. The method according to claim 10, wherein a longitudinal size of the solder connection, after flowing is determined by a longitudinal dimension of the pad metal containing layer or the opening.

16. The method according to claim 1, wherein, after the etching, the remaining first metal containing layer and the pad metal containing layer form a ball limiting metallurgical (BLM) layer.

17. The method according to claim 1, wherein the flowing of the solder comprises a multitude of solder connections formed from a mold comprising solder material.

18. The method according to claim 1, wherein the pad metal containing layer or bilayer acts as a mask to an underlying layer during the etching.

19. The method according to claim 1, wherein the etching is a dry etching which preserves a dimensional integrity of the first metal containing layer thereby preventing undercut.

20. A method for reducing corrosion of under bump metallization material during formation of a solder bump on a semiconductor structure comprising:

forming a passivated layer with a trench over at least a metallized layer in a structure;

forming a first metal containing layer within the trench;

controlling a size of at least a second metal containing layer by patterned resist;

etching the patterned resist and portions of the first metal containing layer under the patterned resist, while protecting remaining portions of the first metal containing layer with the second metal containing layer; and

reflowing solder material on the second metal containing layer to form a solder bump, wherein of the first metal containing layer is substantially devoid of an undercut, controlled during the etching step.

21. The method according to claim 20, wherein the solder material is attached prior to etching of the resist and is used as a mask.

22. The method according to claim 20, wherein the solder bump has a dimensional size of the second metal containing layer, controlled by the resist pattern.

23. The method according to claim 20, wherein solder material is formed from a mold comprising solder material at locations that overlap with the trench of the passivated layer.

24. A method for controlling dimensions of a solder bump during formation of the solder bump comprising:

forming a resist pattern having at least one opening configured for solder bumps;

electroplating a metal layer within the at least one opening;

removing the resist pattern and an underlying metal layer;

providing solder material on the electroplated metal; and

reflowing the solder material to form a solder bump.

25. The method according to claim 24, wherein the solder material is filled before the resist pattern is removed.

26. The method according to claim 25, wherein the solder material is used as a mask for etching.

27. The method according to claim 24, wherein the at least one opening limits longitudinal dimensions of the electroplated material.

28. The method according to claim 27, wherein the longitudinal dimensions of the electroplated material sets dimensions of the solder bump.

29. A method comprising:

sputtering a first metal containing layer onto a structure having a metal formation;

forming a passivation layer over the first metal containing layer having a trench in alignment with the metal formation;

patterning a resist on the passivation layer to form opening to the first metal containing layer;

electroplating a second metal containing layer in opening bound by the resist;

removing the resist and the first metal layer underlying the resist, using the second metal containing layer as a mask;

attaching solder material onto the second metal containing layer; and

reflowing the solder material.

30. A controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form ball limiting metallurgical layers and an underlying metal layer devoid of undercuts.

31. The structure according to claim 30, comprising a multitude of electroplated metal layers that are separated by the resist pattern.

32. The structure according to claim 30, wherein the solder material is formed on the electroplated metal layer.

33. A structure comprising a passivated layer with a trench over at least a metallized layer in a structure, a first metal containing layer within the trench and contacting a back of the end process metal layer, an electroplated metal dimensionally controlled by a patterned resist overlying the first metal containing layer and a solder material reflowed on the electroplated metal containing layer to form a solder bump, wherein the first metal containing layer is devoid of an undercut.

34. The structure according to claim 33, wherein the first metal containing layer is provided on the passivation layer.

35. The structure according to claim 33, wherein the electroplated metal is copper.