Optimized placement policy for solid state storage devices

• US 20070288686A1
• Filed: 06/08/2006
• Published: 12/13/2007
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Babaylan, Ritchie, Lanuza, Reyjan, Arcedera, Mark
• Granted Patent: US 7,506,098 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A data storage system is provided comprising several flash arrays in a board and stacking these boards to attain a high-capacity solid state hard drive. A remap table is used to map all logical addresses from a host system to the actual physical addresses where data are stored. The assignments of these physical locations are done in such a way that the load of the system is evenly distributed to its available resources. This would ensure that the storage system will run at its utmost efficiency utilizing its resources properly. To achieve this, the system would make sure that the physical location of data be evenly distributed according to the current load of the system.

Claims

1. Apparatus for data storage comprising:

a plurality of flash buses;

a plurality of DMA engines coupled to at lease two of the plurality of flash buses; and

a plurality of flash chips coupled to at least two of the plurality of DMA engines;

wherein data access performance is improved by bus interleaving wherein one or more data is transferred to or from the plurality of flash chips using at least two flash buses;

wherein data access performance is improved by flash array bank interleaving wherein one or more data is transferred to or from the plurality of flash chips using at least two DMA engines; and

wherein data access performance is improved by group interleaving wherein one or more data is transferred to or from the plurality of flash chips using at least two flash chips.

2. The apparatus of claim 1:

wherein each of the plurality of flash chips further comprises a plurality of sections;

wherein each section in the apparatus is operable to be accessed using a physical block address comprising a least significant portion, a second least significant portion, a third least significant portion, and a fourth least significant portion;

wherein the least significant portion comprises an order according to the plurality of flash buses, the second least significant portion comprises an order according to a plurality of DMA engines each coupled to a same flash bus, the third least significant portion comprises an order according to a plurality of flash chips each coupled to a same DMA engine, and the fourth least significant portion comprises an order according to the plurality of sections in a same flash chip; and

wherein a logical block address for host data access is mapped to a physical block address according to a placement algorithm whereby host data access performance is improved.

3. The apparatus of claim 2;

wherein at least one section in at least one of the plurality of flash chips is designated as free section;

wherein at least one free section is pre-erased as target for at least one data relocation whereby flash write performance and bad block replacement performance are improved according to the placement algorithm.

4. The apparatus of claim 3:

wherein the placement algorithm maps each logical block address to a physical block address in a linear mapping prior to the at least one data relocation; and

wherein the placement algorithm designates a plurality of free sections evenly to each of the plurality of flash chips.

5. The apparatus of claim 4, wherein the placement algorithm locates a target for each of the at least one data relocation for write operation according to a current load represented in a system queue based on a priority comprising firstly locating a free section corresponding to a different flash bus, secondly locating a free section corresponding to a different DMA engine coupled to a same flash bus, and thirdly locating a free section corresponding to a different flash chip coupled to a same DMA engine.

6. The apparatus of claim 4, wherein the placement algorithm locates a target for each of the at least one data relocation for bad block management based on a priority comprising firstly locating a free section corresponding to a same flash chip, secondly locating a free section corresponding to a different flash chip coupled to a same DMA engine, and thirdly locating a section corresponding to a different DMA engine coupled to a same flash bus.

7. The apparatus of claim 4;

wherein each section further comprises a plurality of stripes; and

wherein the linear mapping further comprises one or more chip interleaves.