Method for managing and controlling the low power modes for an integrated circuit device

• US 20070288778A1
• Filed: 07/31/2006
• Published: 12/13/2007
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhuang, Zhiqing, Fadavi-Ardekani, Jalil, Kamal, Soheyla, Bhasin, Vinay Kumar, Zhang, Chenmin, Rakshani, Vafa James, Madar, Lawrence John
• Granted Patent: US 7,739,528 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention'"'"'s state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Claims

1. A power management unit to manage low power modes for an electronic IC device comprising:

a sequencer state machine to store voltage levels for multiple power modes including a RUN mode, a HIBERNATE mode and a POWERDOWN mode;

a timer to control wait times between external events that trigger any transitions between the RUN mode, the HIBERNATE mode and the POWERDOWN mode;

a control register set to store information about operating parameters of the power management unit;

a wake up event detection logic to trigger the transition between said multiple power modes; and

a register file to store the settings for the RUN mode, the HIBERNATE mode and the POWERDOWN mode.

2. The power management unit of claim 1, wherein the wake up detection logic runs from a 32 KHz clock.

3. The power management unit of claim 1, wherein the wake up detection logic can respond to at least 16 external wake up events.

4. The power management unit of claim 1, wherein the wake up detection logic gets triggered whenever a voltage level change from a High to a Low or a Low to a High occurs.

5. The power management unit of claim 1, wherein the RUN mode is the only operating state in which the processor runs code.

6. The power management unit of claim 1, wherein in the RUN mode, the state machine operates in the voltage range of 0.9 Volts to 1.2 Volts.

7. The power management unit of claim 1, wherein the power management unit includes a random access memory to store information about the multiple power modes.

8. The power management unit of claim 1, wherein in the POWERDOWN mode, the state machine operates at zero voltage.

9. The power management unit of claim 1, wherein the control register set includes programmable registers controlled by a high speed clock which can be gated off after the programmable registers have been programmed.

10. The power management unit of claim 1, wherein the control register set has a security key to prevent any malicious programming attempts.

11. The power management unit of claim 1, wherein the register file stores operating voltage settings for transitions between the RUN mode, the POWERDOWN mode and the HIBERNATE mode.

12. The power management unit of claim 1, wherein the power management unit is driven by a low frequency clock operating at a frequency substantially equal to 32 KHz.

13. The power management unit of claim 1, wherein the control register set receives commands from an external processor.

14. The power management unit of claim 1, wherein the sequencer state machine also stores commands written by an external host.

15. The power management unit of claim 1, wherein the power management unit further includes an I2C bus driver to drive an external power management unit via an I2C bus.

16. The power management unit of claim 1, wherein the power management unit further includes input and output lines to communicate with an external processor via a set of interface signals.

17. The power management unit of claim 9, further including an external clock manager to start and stop the high speed clocks.

18. The power management unit of claim 12, further including an external clock manager to start and stop the low frequency clock.

19. The power management unit of claim 1, wherein said control register set includes bits to provide a security access code to access the control register set.

20. The power management unit of claim 9, wherein the control register set is run by the high speed clock.

21. The power management unit of claim 1, wherein said power management unit supports write to an external power management unit using said I2C bus.

22. A method to securely perform transitions between various power modes of an IC comprising:

assigning a respective voltage level range to multiple power modes including

a first RUN mode,

a HIBERNATE mode,

a POWERDOWN mode, and

a second RUN mode operating at a voltage level different from the first RUN mode;

changing from a first voltage level to a second voltage level;

transitioning from one power mode to another power mode; and

controlling transitions between the multiple power modes by changing between a range of voltage levels.

23. The method of claim 22 wherein transitioning from the first RUN mode to the POWERDOWN mode further involves the steps of:

(a) stopping all unnecessary clocks and power supplies;

(b) counting down to zero from a pre-programmed value;

(c) stopping counting before zero is reached, if an external event is detected;

(d) sending a request to a clock manager, if count is at zero;

(e) waiting for an acknowledgement from the clock manager;

(f) switching to a voltage level corresponding to the POWERDOWN mode, if the count is at zero; and

(g) monitoring any external event after switching to said voltage level.

24. The method of claim 22, wherein transitioning from the POWERDOWN mode to the first RUN mode further involves the steps of:

(a) detecting a wake up event; and

(b) switching to a voltage level corresponding to the first RUN mode.

25. The method of claim 22, wherein transitioning from the first RUN mode to the HIBERNATE mode further involves the steps of:

(a) stopping all unnecessary clocks;

(b) counting down to zero from a pre-programmed value;

(c) stopping counting before zero is reached, if an external event is detected;

(d) sending a request to a clock manager, if count is at zero;

(e) waiting for an acknowledgement from the clock manager;

(f) switching to a voltage level corresponding to the HIBERNATE mode, if the count is at zero; and

(g) monitoring any external event after switching to said voltage level.

26. The method of claim 22, wherein transitioning from the HIBERNATE mode to the first RUN mode further involves the steps of:

(a) detecting a wake up event; and

(b) switching to a voltage level corresponding to the first RUN mode.

27. The method of claim 22, wherein transitioning from the HIBERNATE mode to the POWERDOWN mode further involves the steps of:

(a) counting down to zero from a pre-programmed value;

(b) switching to a voltage level corresponding to the POWERDOWN mode;

(c) ignoring any external event until the switching is complete; and

(d) monitoring for any external event after switching to said voltage level.

28. The method of claim 22, wherein transitioning from the first RUN mode to the second RUN mode further involves the steps of:

(a) switching to a voltage level corresponding to the second RUN mode; and

(b) ignoring any external event until the switching is complete.