Power consumption decrease memory management method

• US 20070288783A1
• Filed: 03/30/2007
• Published: 12/13/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sugita, Yumiko, Ogasawara, Katsuhisa
• Granted Patent: US 7,793,129 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3225 of memory devices

Abstract

The power consumed by a memory is reduced without affecting the performance whereby a processor accesses the memory. A state of a power supplied to the memory is controlled to one of an active state wherein a storage area included in the memory rank can be accessed from the processor, and an inactive state wherein access cannot be performed without a delay for each memory rank, the basic system software prevents fragmentation in which the allocated storage area spans a plurality of memory ranks, puts the power state of a memory rank which does not include an allocated storage area into the inactive state, and puts the power state of a memory rank which includes a storage area required for allocation first into the active state.

Claims

1. A memory management method performed in a computer having at least one processor which executes basic system software, firmware and application software, a memory which is a storage area, and a memory controller coupled to the memory,

wherein the memory controller controls a memory addressing which defines an address in the memory, a memory access from the processor to the memory and a memory power state,

wherein the memory storage area is an area which can be assigned to the basic system software, the firmware and the application software, the storage area is divided into memory ranks which are units whose power can be independently controlled by the memory controller,

wherein a supplied power state of the memory is controlled, for each memory rank, to one of an active state in which the storage area included in the memory rank can be accessed from the processor, and an inactive state in which access from the processor to the storage area is delayed;

and

wherein the basic system software prevents fragmentation in which the allocated storage area spans a plurality of memory ranks, puts the power state of a memory rank which does not include the allocated storage area into the inactive state via the memory controller, and puts the power state of a memory rank which includes a storage area required for the allocation first into the active state.

2. The memory management method according to claim 1, wherein the basic system software determines whether the unallocated storage area is included in the memory rank in the active state, and allocates an unallocated storage area included in a memory rank in the active state to the basic system software, firmware and application software.

3. The memory management method according to claim 1, wherein the basic system software calculates a prediction value of an allocation area, and puts the power state of the memory rank into the active state first based on the predicted value.

4. The memory management method according to claim 1, wherein the basic system software selects the memory rank including a small allocable size from among memory ranks whose power state is the inactive state, and puts the selected memory rank into the active state first via the memory controller.

5. The memory management method according to claim 1,

wherein the basic system software manages a potential table for each memory rank of each memory showing a memory potential value which is the sum of a value obtained by multiplying a delay time whereby said processor accesses the memory by a predetermined position potential coefficient, and a value obtained by multiplying a power potential showing the power state of the memory rank by a predetermined power potential coefficient;

and

wherein the basic system software selects the memory rank of the memory for which the memory potential value is a minimum by referring to the potential table, and allocates an unallocated storage area included in the selected memory rank to the basic system software, the firmware and the application software.

6. A computer readable medium storing a program executed by a computer which executes a sequence for memory management, the program being executed by the computer comprising at least one processor which executes basic system software, firmware and application software, a memory which is a storage area, and a memory controller coupled to the memory,

wherein the memory controller controls a memory addressing which defines an address in the memory, a memory access from the processor to the memory and a memory power state,

wherein the memory storage area is an area which can be allocated to the basic system software, the firmware and the application software, the storage area is divided into memory ranks which are units whose power can be independently controlled by the memory controller,

wherein a supplied power state of the memory is controlled, for each memory rank, to one of an active state in which the storage area included in the memory rank can be accessed from the processor, and an inactive state in which access from the processor to the storage area is delayed, and

wherein the program including the sequence of instructions that, in case of which the program is executed, causes the computer to:

prevent fragmentation in which the allocated storage area spans a plurality of memory ranks;

put the power state of a memory rank which does not include the allocated storage area into the inactive state via the memory controller; and

put the power state of a memory rank which includes a storage area required for said allocation first into the active state.

7. The computer readable medium storing the program according to claim 6, wherein the program including the sequence of instructions that causes the computer to:

determine whether the unallocated storage area is included in the memory rank in the active state; and

allocate an unallocated storage area included in a memory rank in the active state to the basic system software, firmware and application software.

8. The computer readable medium storing the program according to claim 6, wherein the program including the sequence of instructions that causes the computer to:

calculate a prediction value of an allocation area; and

put the power state of the memory rank into the active state first based on the predicted value.

9. The computer readable medium storing the program according to claim 6, wherein the program including the sequence of instructions that causes the computer to:

select the memory rank including a small allocable size from among memory ranks whose power state is the inactive state; and

put the selected memory rank into the active state first via the memory controller.

10. The computer readable medium storing the program according to claim 6, wherein the program including the sequence of instructions that causes the computer to:

manage a potential table for each memory rank of each memory showing a memory potential value which is the sum of a value obtained by multiplying a delay time whereby said processor accesses the memory by a predetermined position potential coefficient, and a value obtained by multiplying a power potential showing the power state of the memory rank by a predetermined power potential coefficient; and

select the memory rank of the memory for which the memory potential value is a minimum by referring to the potential table; and

allocate an unallocated storage area included in the selected memory rank to the basic system software, the firmware and the application software.