Timing-aware test generation and fault simulation

• US 20070288822A1
• Filed: 04/27/2007
• Published: 12/13/2007
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Lin, Xijiang, Tsai, Kun-Han, Kassab, Mark, Wang, Chen, Rajski, Janusz
• Granted Patent: US 8,051,352 B2
• Time in Patent Office: Days
• US Class Current: 714/741
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318328 for delay tests
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Claims

1. A method of generating test patterns for testing an integrated circuit, comprising:

identifying two or more possible fault propagation paths in an integrated circuit design, the possible fault propagation paths being capable of propagating a fault effect of a targeted delay fault to an observation point in the integrated circuit design;

selecting one of the possible fault propagation paths using a weighted random selection procedure;

generating test pattern values that propagate the fault effect on the selected fault propagation path; and

storing the test pattern values.

2. The method of claim 1, wherein the weighted random selection procedure favors fault propagation paths with longer path delays over fault propagation paths with shorter path delays.

3. The method of claim 1, wherein the weighted random selection procedure favors fault propagation paths with shorter path delays over fault propagation paths with longer path delays.

4. The method of claim 1, further comprising computing weights for each of the possible fault propagation paths.

5. The method of claim 4, wherein the computed weight for a respective one of the possible fault propagation paths indicates the probability that the respective one of the possible fault propagation paths will be selected by the weighted random selection procedure.

6. The method of claim 4, wherein the act of computing weights comprises computing a weight w_i for a respective possible fault propagation path i as follows:

$w_i=\frac{{\mathrm{PT}}_i^s}{\underset{i=1}{\overset{n}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\mathrm{PT}}_i^s<br><br>\text{\hspace{1em}<br><br>}},$

where n is the number of possible fault propagation paths, i is an index value, and PT_i^s is the longest static propagation time for the possible fault propagation path i.

7. The method of claim 4, wherein the act of computing weights comprises computing a weight w_i for a respective possible fault propagation path i as follows:

$w_i=\frac{\frac{1}{{\mathrm{HPT}}_i^s}}{\underset{i=1}{\overset{n}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>\frac{1}{{\mathrm{HPT}}_i^s}},$

where n is the number of possible fault propagation paths, i is an index value, and HPT_i^s is the shortest static propagation time for the possible fault propagation path i

8. The method of claim 1, wherein the method further comprises computing propagation times for one or more gates in the possible fault propagation paths, and wherein the weighted random selection procedure is based at least in part on the computed propagation times.

9. The method of claim 8, wherein the act of computing the propagation times comprises using timing information from an SDF file.

10. The method of claim 1, further comprising selecting a fault activation condition for activating the targeted delay fault using a weighted random selection procedure that favors fault activation conditions having longer arrival times over fault activation conditions having shorter arrival times.

11. The method of claim 1, further comprising selecting a fault activation condition for activating the targeted delay fault using a weighted random selection procedure that favors fault activation conditions having shorter arrival times over fault activation conditions having longer arrival times.

12. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 1.

13. One or more computer-readable media storing test pattern values generated by the method of claim 1.

14. A method of generating test patterns for testing an integrated circuit, comprising:

identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design;

selecting one of the possible fault activation conditions using a weighted random selection procedure;

generating test pattern values that activate the targeted delay fault at the fault site with the selected fault activation conditions; and

storing the test pattern values.

15. The method of claim 14, wherein the weighted random path selection procedure favors paths with longer arrival times to the targeted delay fault site over paths with shorter arrival times to the targeted delay fault site.

16. The method of claim 14, wherein the weighted random path selection procedure favors paths with shorter arrival times to the targeted delay fault site over paths with longer arrival times to the targeted delay fault site.

17. The method of claim 14, further comprising computing weights for each of the possible fault activation conditions.

18. The method of claim 17, wherein the computed weight for a respective one of the possible fault activation conditions indicates the probability that the respective one of the possible fault activation conditions will be selected by the weighted random selection procedure.

19. The method of claim 17, wherein the act of computing comprises computing a weight w_i for a respective possible fault activation condition i as follows:

$w_i=\frac{{\mathrm{AT}}_i^s}{\underset{i=1}{\overset{n}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>{\mathrm{AT}}_i^s},$

where n is the number of possible fault activation conditions, i is an index value, and AT_i^s is the longest static arrival time to the ith choice to justify the gate.

20. The method of claim 17, wherein the act of computing comprises computing a weight w_i for a respective possible fault activation condition i as follows:

$w_i=\frac{\frac{1}{{\mathrm{HAT}}_i^s}}{\underset{i=1}{\overset{n}{\sum <br><br>}}<br><br>\text{\hspace{1em}<br><br>}<br><br>\frac{1}{{\mathrm{HAT}}_i^s}},$

where n is the number of possible fault activation conditions, i is an index value, and HAT_i^s is the shortest static arrival time to the ith choice to justify the gate.

21. The method of claim 14, wherein the method further comprises computing activation times for one or more gates in the paths used with the possible fault activation conditions, and wherein the weighted random selection procedure is based at least in part on the computed activation times.

22. The method of claim 21, wherein the act of computing the activation times comprises using timing information from an SDF file.

23. The method of claim 14, further comprising selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having longer propagation times over fault propagation paths having shorter propagation times.

24. The method of claim 14, further comprising selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having shorter propagation times over fault propagation paths having longer propagation times.

25. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 14.

26. One or more computer-readable media storing test pattern values generated by the method of claim 14.

27. A method of generating test patterns for testing an integrated circuit, comprising:

identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;

computing an actual path delay for the identified fault;

determining that the identified fault is to be removed from a fault list, the determination being based at least in part on the computed actual path delay;

modifying the fault list by removing the identified fault; and

storing the modified fault list.

28. The method of claim 27, wherein the determination is further based at least in part on the static path delay.

29. The method of claim 28, wherein the determination is based at least in part on a relative difference between actual slack and static slack of the longest sensitized path detecting the fault, the actual slack being determined by the actual path delay through the longest sensitized path detecting the fault and the static slack being determined by the static path delay through the longest sensitized path detecting the fault.

30. The method of claim 29, wherein the act of determining comprises determining whether the difference satisfies a user-selected criteria.

31. The method of claim 27, wherein the act of determining comprises determining that the following condition is met:

$\frac{{\mathrm{PD}}_f^s-{\mathrm{PD}}_f^a}{T_{\mathrm{TC}}-{\mathrm{PD}}_f^a}<<br><br>\mathrm{\delta <br><br>},$

where PD_f^s is the static path delay for the fault f, PD_f^a is the actual path delay for the fault, T_TC is the test clock period, and δ

is a real number between 0 and 1.

32. The method of claim 31, wherein δ

is user-selectable.

33. The method of claim 28, wherein the determination is based at least in part on a relative difference between actual slack and static slack of the shortest sensitized path detecting the fault, the actual slack being determined by the actual path delay through the shortest sensitized path detecting the fault and the static slack being determined by the static path delay through the shortest sensitized path detecting the fault.

34. The method of claim 33, wherein the act of determining comprises determining whether the difference satisfies a user-selected criteria.

35. The method of claim 27, wherein the act of determining comprises determining that the following condition is met:

$\frac{{\mathrm{HPD}}_f^a-{\mathrm{HPD}}_f^s}{T_{\mathrm{TC}}-{\mathrm{HPD}}_f^s}<<br><br>\mathrm{\delta <br><br>},$

where HPD_f^s is the static path delay through the shortest sensitized path for the fault f, HPD_f^a is the actual path delay through the shortest sensitized path for the fault, T_TC is the test clock period, and δ

is a real number between 0 and 1.

36. The method of claim 35, wherein δ

is user-selectable.

37. The method of claim 27, wherein the method is repeated for additional faults in the fault list not detected by previously generated test patterns.

38. The method of claim 27, wherein the act of identifying further comprises:

performing a good machine simulation to determine a response of the integrated circuit design to the test pattern in the absence of any faults; and

identifying one or more paths sensitized by the test pattern.

39. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 27.

40. One or more computer-readable media storing a fault list created by the method of claim 27.

41. A method of generating test patterns for testing an integrated circuit, comprising:

identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;

computing a static path delay for a selected sensitized path through the identified fault;

determining whether a criterion based at least in part on the static path delay is met for the identified fault;

modifying the fault list by removing the identified fault if the criterion is met; and

storing the modified fault list.

42. The method of claim 41, wherein the selected sensitized path is the longest sensitized path.

43. The method of claim 42, wherein the act of determining whether the criterion is met comprises determining whether:

$\frac{T_{\mathrm{TC}}-{\mathrm{PD}}_f^s}{T_{\mathrm{TC}}}\ge <br><br>\mathrm{\lambda <br><br>}$

where PD_f^s is the static path delay through the longest sensitized path for the fault f, T_TC is the test clock period, and λ

is a real number between 0 and 1.

44. The method of claim 41, wherein the selected sensitized path is the shortest sensitized path.

45. The method of claim 44, wherein the act of determining whether the criterion is met comprises determining whether:

$\frac{T_{\mathrm{TC}}-{\mathrm{HPD}}_f^s}{T_{\mathrm{TC}}}<<br><br>\mathrm{\lambda <br><br>}$

where HPD_f^s is the static path delay through the shortest sensitized path for the fault f, T_TC is the test clock period, and λ

is a real number between 0 and 1.

46. The method of claim 41, wherein the criterion is a first criterion, and wherein the method further comprises:

computing an actual path delay for the selected sensitized path through the identified fault;

determining whether a second criterion based at least in part on the actual path delay is met for the identified fault; and

modifying the fault list by removing the identified fault if the first criterion is not met but the second criterion is met.

47. The method of claim 46, wherein the act of determining whether the second criterion is met comprises determining whether:

$\frac{{\mathrm{PD}}_f^s-{\mathrm{PD}}_f^a}{T_{\mathrm{TC}}-{\mathrm{PD}}_f^a}<<br><br>\mathrm{\delta <br><br>},$

where PD_f^s is the static path delay through the longest sensitized path for the fault f, PD_f^a is the actual path delay through the longest sensitized path for the fault, T_TC is the test clock period, and δ

is a real number between 0 and 1.

48. The method of claim 46, wherein the act of determining whether the second criterion is met comprises determining whether:

$\frac{{\mathrm{HPD}}_f^a-{\mathrm{HPD}}_f^s}{T_{\mathrm{TC}}-{\mathrm{HPD}}_f^s}<<br><br>\mathrm{\delta <br><br>},$

where HPD_f^s is the static path delay through the shortest sensitized path for the fault f, HPD_f^a is the actual path delay through the shortest sensitized path for the fault, T_TC is the test clock period, and δ

is a real number between 0 and 1.

49. The method of claim 41, wherein the method is repeated for additional faults in the fault list not detected by previously generated test patterns.

50. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 41.

51. One or more computer-readable media storing a fault list created by the method of claim 41.

52. A method of generating test patterns for testing an integrated circuit, comprising:

simulating a response of an integrated circuit design to a test pattern in the absence of any faults in the integrated circuit design;

identifying paths sensitized by the test pattern by backward tracing from the observation points of the integrated circuit design and analyzing sensitization conditions in the integrated circuit design, the sensitization conditions including reconvergent path sensitization conditions;

identifying a fault detected by the test pattern by simulating a response of the integrated circuit design to the test pattern in the presence of the fault and determining that one or more of the identified paths detect the fault;

determining a path delay for the one or more paths that detect the fault; and

storing the path delay.

53. The method of claim 52, wherein the path delay is computed using the longest propagation time in the identified paths.

54. The method of claim 52, wherein the path delay is a current path delay, and wherein the act of storing the path delay comprises:

comparing the current path delay to a previously stored path delay associated with the fault; and

replacing the previously stored path delay with the current path delay if the current path delay is longer.

55. The method of claim 52, wherein the path delay is computed using the shortest propagation time in the identified paths.

56. The method of claim 52, wherein the path delay is a current path delay, and wherein the act of storing the path delay comprises:

comparing the current path delay to a previously stored path delay associated with the fault; and

replacing the previously stored path delay with the current path delay if the current path delay is shorter.

57. The method of claim 52, wherein the path delay is the actual path delay.

58. The method of claim 57, further comprising:

computing an actual slack time using the actual path delay; and

removing the fault from a fault list if a user-selected criterion based at least in part on the actual slack time is met.

59. The method of claim 52, wherein the act of identifying paths comprises identifying reconvergent sensitization paths.

60. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 52.