×

Timing-aware test generation and fault simulation

  • US 20070288822A1
  • Filed: 04/27/2007
  • Published: 12/13/2007
  • Est. Priority Date: 04/27/2006
  • Status: Active Grant
First Claim
Patent Images

1. A method of generating test patterns for testing an integrated circuit, comprising:

  • identifying two or more possible fault propagation paths in an integrated circuit design, the possible fault propagation paths being capable of propagating a fault effect of a targeted delay fault to an observation point in the integrated circuit design;

    selecting one of the possible fault propagation paths using a weighted random selection procedure;

    generating test pattern values that propagate the fault effect on the selected fault propagation path; and

    storing the test pattern values.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×