Top layers of metal for high performance IC's

• US 20070288880A1
• Filed: 08/17/2007
• Published: 12/13/2007
• Est. Priority Date: 12/21/1998
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, Mou-Shiung
• Application Number:
  US11/893,659
• Publication Number:
  US 20070288880A1
• Time in Patent Office: Days
• US Class Current: 716/130
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:

determining if an interconnection has a length exceeding a pre-determined length; and

routing said interconnection having said length exceeding said pre-determined length through said second metallization structure over said passivation layer.

2. The routing method of claim 1, wherein said second metallization structure comprises an upper metal line having a width greater than that of a lower metal line of said first metallization structure.

3. The routing method of claim 1, wherein said second metallization structure comprises an upper metal layer having a thickness greater than that of a lower metal layer of said first metallization structure.

4. The routing method of claim 1, wherein said second metallization structure comprises an electroplated metal.

5. The routing method of claim 1, wherein said first metallization structure comprises aluminum.

6. The routing method of claim 1, wherein said first metallization structure comprises electroplated copper.

7. The routing method of claim 1, wherein said integrated circuit chip comprises a polymer layer over said passivation layer.

8. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:

determining if an interconnection has a parameter exceeding a pre-determined value; and

routing said interconnections having said parameter exceeding said pre-determined value over a passivation layer.

9. The routing method of claim 8, wherein said second metallization structure comprises an upper metal line having a width greater than that of a lower metal line of said first metallization structure.

10. The routing method of claim 8, wherein said second metallization structure comprises an upper metal layer having a thickness greater than that of a lower metal layer of said first metallization structure.

11. The routing method of claim 8, wherein said second metallization structure comprises an electroplated metal.

12. The routing method of claim 8, wherein said first metallization structure comprises aluminum.

13. The routing method of claim 8, wherein said first metallization structure comprises electroplated copper.

14. The routing method of claim 8, wherein said integrated circuit chip comprises a polymer layer over said passivation layer.

15. A computer based routing tool for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:

means for determining if an interconnection has a length exceeding a pre-determined length; and

means for routing said interconnections having said length exceeding said pre-determined length over a passivation layer.

16. The computer based routing tool of claim 15, wherein said second metallization structure comprises an upper metal line having a width greater than that of a lower metal line of said first metallization structure.

17. The computer based routing tool of claim 15, wherein said second metallization structure comprises an upper metal layer having a thickness greater than that of a lower metal layer of said first metallization structure.

18. The computer based routing tool of claim 15, wherein said second metallization structure comprises an electroplated metal.

19. The computer based routing tool of claim 15, wherein said first metallization structure comprises aluminum.

20. The computer based routing tool of claim 15, wherein said first metallization structure comprises electroplated copper.

21. The computer based routing tool of claim 15, wherein said integrated circuit chip comprises a polymer layer over said passivation layer.

22. A computer based routing tool for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:

means for determining if an interconnection has a parameter exceeding a pre-determined value; and

means for routing said interconnections having said parameter exceeding said pre-determined value over a passivation layer.

23. The computer based routing tool of claim 22, wherein said second metallization structure comprises an upper metal line having a width greater than that of a lower metal line of said first metallization structure.

24. The computer based routing tool of claim 22, wherein said second metallization structure comprises an upper metal layer having a thickness greater than that of a lower metal layer of said first metallization structure.

25. The computer based routing tool of claim 22, wherein said second metallization structure comprises an electroplated metal.

26. The computer based routing tool of claim 22, wherein said first metallization structure comprises aluminum.

27. The computer based routing tool of claim 22, wherein said first metallization structure comprises electroplated copper.

28. The computer based routing tool of claim 22, wherein said integrated circuit chip comprises a polymer layer over said passivation layer.