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Top layers of metal for high performance IC's

  • US 20070288880A1
  • Filed: 08/17/2007
  • Published: 12/13/2007
  • Est. Priority Date: 12/21/1998
  • Status: Abandoned Application
First Claim
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1. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:

  • determining if an interconnection has a length exceeding a pre-determined length; and

    routing said interconnection having said length exceeding said pre-determined length through said second metallization structure over said passivation layer.

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