Top layers of metal for high performance IC's
First Claim
1. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:
- determining if an interconnection has a length exceeding a pre-determined length; and
routing said interconnection having said length exceeding said pre-determined length through said second metallization structure over said passivation layer.
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Accused Products
Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
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Citations
28 Claims
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1. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:
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determining if an interconnection has a length exceeding a pre-determined length; and
routing said interconnection having said length exceeding said pre-determined length through said second metallization structure over said passivation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A routing method for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:
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determining if an interconnection has a parameter exceeding a pre-determined value; and
routing said interconnections having said parameter exceeding said pre-determined value over a passivation layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer based routing tool for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:
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means for determining if an interconnection has a length exceeding a pre-determined length; and
means for routing said interconnections having said length exceeding said pre-determined length over a passivation layer. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A computer based routing tool for designing an integrated circuit chip to be fabricated comprising a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, and a second metallization structure over said passivation layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, comprising:
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means for determining if an interconnection has a parameter exceeding a pre-determined value; and
means for routing said interconnections having said parameter exceeding said pre-determined value over a passivation layer. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification