STRUCTURE AND METHOD FOR FORMING A SHIELDED GATE TRENCH FET WITH THE SHIELD AND GATE ELECTRODES BEING CONNECTED TOGETHER

• US 20070290257A1
• Filed: 06/19/2006
• Published: 12/20/2007
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Thorup, Paul, Kocon, Christopher Boguslaw, Kraft, Nathan
• Granted Patent: US 7,319,256 B1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween, wherein the shield electrode and the gate electrode are electrically connected together.

Claims

1. A field effect transistor (FET) comprising:

a trench extending into a semiconductor region;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric (IED) over the shield electrode; and

a gate electrode in an upper portion of the trench over the IED, the gate electrode being insulated from the semiconductor region by a gate dielectric, wherein the shield electrode is electrically connected to the gate electrode,

wherein the trench extends in an active region of the FET, the shield electrode and gate electrode extending out of the trench and into a non-active region of the FET where the shield electrode and gate electrode are electrically connected together by a first interconnect layer.

2. The FET of claim 1 wherein the semiconductor region comprises:

a drift region of a first conductivity type;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type in the body region adjacent to the trench.

3. The FET of claim 2 wherein the gate electrode is recessed in the trench to below a top surface of the semiconductor region, the FET further comprising:

a second interconnect layer contacting the source and body regions; and

a dielectric material over the gate electrode for insulating the gate electrode and the interconnect layer from one another.

4. The FET of claim 2 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein the trench extends through the body region and terminates within the drift region.

5. The FET of claim 2 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein the trench extends through the body region and the drift region and terminates within the substrate.

7. The FET of claim 2 wherein the electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.

8. The FET of claim 2 wherein the shield electrode is electrically connected to the gate electrode by an additional connection through the IED in the trench.

9. The FET of claim 1 wherein the gate electrode is electrically connected to the shield electrode through at least one opening in the IED inside the trench.

10. The FET of claim 1 wherein the non-active region includes a termination region extending along a perimeter of a die housing the FET, the electrical connection between the shield electrode and gate electrode being made in the termination region.

11. The FET of claim 10 wherein the electrical connection between the shield and gate electrodes is made through one or more contact openings in the termination region.

6. (canceled)

12. A field effect transistor (FET) in a semiconductor die comprising:

an active region housing active cells;

a non-active region with no active cells therein;

a drift region of a first conductivity type;

a body region of a second conductivity type over the drift region; and

a plurality of trenches extending through the body region and into the drift region, each trench including a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode;

wherein the shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.

13. The FET of claim 12 furhter comprising:

source regions of the first conductivity type in the body region adjacent to each trench; and

heavy body regions of the second conductivity type in the body region adjacent the source regions.

14. The FET of claim 13 wherein the gate electrode is recessed in the trench to below a top surface of the source regions, the FET further comprising:

an interconnect layer contacting the source regions and heavy body regions; and

a dielectric material over the gate electrode for insulating the gate electrode and the interconnect layer from one another.

15. The FET of claim 12 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein the trench terminates within the drift region.

16. The FET of claim 12 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein each trench terminates within the substrate.

17. The FET of claim 12 further comprising an inter-electrode dielectric between the shield electrode and the gate electrode in each trench, wherein the shield electrode is electrically connected to the gate electrode by an additional connection through the inter-electrode dielectric.

18. The FET of claim 12 wherein the non-active region includes a gate runner region extending through a middle portion of the die, the shield electrode and gate electrode extending out of each trench and into the gate runner region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer.

19. The FET of claim 12 wherein the non-active region includes a termination region extending along a perimeter of the die, the shield electrode and gate electrode extending out of each trench and into the termination region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer.

20. A field effect transistor (FET) comprising a plurality of trenches extending into a semiconductor region, each trench having a gate electrode and a shield electrode with an inter-electrode dielectric therebetween, wherein the shield electrode and the gate electrode are electrically connected together in a non-active region of the FET.

21-30. -30. (canceled)