Package of MEMS device and method for fabricating the same

• US 20070290308A1
• Filed: 06/13/2007
• Published: 12/20/2007
• Est. Priority Date: 06/14/2006
• Status: Active Grant

• Current Assignee: Atria Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Dong-Joon, Pyo, Sung-Gyu
• Granted Patent: US 7,615,394 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Claims

1. A package of a micro-electro-mechanical systems (MEMS) device, the package comprising:

a cap wafer;

a plurality of bonding bumps formed over the cap wafer;

a plurality of array pads arrayed on an outer side of the bonding bumps; and

an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

2. The package of claim 1, further comprising a sealing line formed between the bonding bumps and the array pads to encompass the bonding bumps.

3. The package of claim 2, wherein the bonding bumps and the sealing line are formed substantially at the same layer level.

4. The package of claim 2, wherein the cap wafer comprises:

a plurality of inner pads;

a plurality of outer pads;

a plurality of inner interconnection lines respectively coupling the inner pads to the outer pads;

an insulation layer covering the inner pads, the outer pads, and the inner interconnection lines;

a plurality of first plugs formed in the insulation layer and respectively coupling the inner pads to the bonding bumps; and

a plurality of second plugs formed in the insulation layer and respectively coupling the outer pads to the array pads.

5. The package of claim 4, wherein the inner pads, the outer pads, and the inner interconnection lines are formed substantially at the same layer level.

6. The package of claim 4, wherein the first plugs and the second plugs are formed substantially at the same layer level.

7. The package of claim 2, wherein the MEMS device wafer comprises:

a silicon on insulator (SOI) substrate;

an insulation layer formed over the SOI substrate;

a plurality of inner pads formed over the insulation layer;

a plurality of barrier walls separated from the inner pads and bonded to the sealing line; and

a moving part supported by the inner pads.

8. The package of claim 7, wherein the inner pads are bonded to the respective bonding bumps.

9. The package of claim 7, wherein the moving part is formed between the barrier walls.

10. The package of claim 7, wherein the inner pads, the barrier walls, and the moving part each include substantially the same material.

11. The package of claim 10, wherein the inner pads, the barrier walls, and the moving part each include a silicon-based material.

12. The package of claim 7, wherein the cap wafer and the MEMS device wafer are separated to a certain distance by the sealing line and the barrier walls.

13. The package of claim 7, wherein the inner pads are bonded to the respective bonding bumps through a bonding promoter.

14. The package of claim 7, wherein the barrier walls are bonded to the sealing line through a bonding promoter.

15. The package of claim 13, wherein the bonding promoter includes one selected from a TiW/Au structure, a Ti/Al structure, a Ti/TiN/Al structure, and a TiN/Al structure.

16. The package of claim 14, wherein the bonding promoter includes one selected from a TiW/Au structure, a Ti/Al structure, a Ti/TiN/Al structure, and a TiN/Al structure.

17. The package of claim 1, wherein the bonding bumps are formed to have substantially the same height as the sealing line.

18. The package of claim 17, wherein the bonding bumps are formed thicker than the array pads.

19. The package of claim 2, wherein the bonding bumps and the sealing line are formed with an area being about 7% to 35% of the total area of the cap wafer.

20. A method for fabricating a package of a micro-electromechanical systems (MEMS) device, the method comprising:

preparing a MEMS device wafer where a first trench is formed;

preparing a cap wafer where a plurality of bonding bumps and a plurality of array pads are formed, the array pads formed in a region corresponding to the first trench and respectively coupled to the bonding bumps through inner interconnection lines;

bonding the MEMS device wafer and the cap wafer to make the first trench and the array pads correspond to each other;

grinding a rear portion of the MEMS device wafer to form an opening line exposing the array pads; and

dicing the MEMS device wafer and the cap wafer.

21. The method of claim 20, wherein preparing the MEMS device wafer comprises:

forming an insulation layer over a silicon on insulator substrate;

forming a silicon-based layer over the insulation layer;

forming a first trench in the silicon-based layer;

forming a second trench deeper than the first trench in the silicon-based layer; and

extending bottom portions of the first and second trenches to form a plurality of inner pads corresponding to the respective bonding bumps, a plurality of barrier walls, and a moving part.

22. The method of claim 21, wherein the second trench is formed to expose the insulation layer.

23. The method of claim 21, wherein forming the first trench comprises performing a sawing process.

24. The method of claim 21, wherein forming the first trench comprises performing an etching process.

25. The method of claim 21, wherein preparing the cap wafer comprises:

forming a plurality of inner pads, a plurality of outer pads, and a plurality of inner interconnection lines over a silicon oxide layer, the inner interconnection lines respectively coupling the inner pads to the outer pads;

forming an insulation layer to cover the inner pads, the outer pads, and the inner interconnection lines;

forming first and second via holes to expose the respective inner and outer pads;

forming a plurality of first and second plugs filling the respective first and second via holes and respectively coupled to the bonding bumps and the array pads;

simultaneously forming the array pads over the respective second plugs and a sealing line between the bonding bumps and the array pads to encompass the bonding bumps; and

forming the bonding bumps over the respective first plugs.

26. The method of claim 25, wherein the bonding bumps are formed thicker than the array pads.

27. The method of claim 25, wherein the bonding bumps include one selected from a group consisting of Au, Ni, and Cu.

28. The method of claim 25, wherein the first trench is formed to a width of about 30 μ

m to 200 μ

m.

29. The method of claim 25, wherein the first trench is formed to a depth of about 100 μ

m to 400 μ

m.

30. The method of claim 25, wherein the bonding bumps have a thickness of about 10 μ

m to 30 μ

m and a width of about 10 μ

m to 100 μ

m.

31. The method of claim 25, wherein bonding the MEMS device wafer and the cap wafer together comprises forming a bonding promoter over the MEMS device wafer.

32. The method of claim 31, wherein the bonding promoter includes one selected from a group consisting of a TiW/Au structure, a Ti/Al structure, a Ti/TiN/Al structure, and a TiN/Al structure.

33. The method of claim 25, wherein bonding the MEMS device wafer and the cap wafer together comprises bonding the bonding bumps to the respective inner pads of the MEMS device wafer, and the sealing line to the barrier walls.