Multi-dimensional wafer-level integrated antenna sensor micro packaging

• US 20070290326A1
• Filed: 10/16/2006
• Published: 12/20/2007
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Space & Mission Systems Corporation (Northrop Grumman Corporation)
• Inventors: Yang, Jeffrey Ming-Jer, Chung, Yun-Ho, Chang-Chien, Patty
• Granted Patent: US 7,615,863 B2
• Time in Patent Office: Days
• US Class Current: 257/697
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1423 Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 13/02 Waveguide horns
• CPC Class Codes: H01Q 3/30 varying the relative phase between the radiating elements of an array H01Q3/2605, H01Q3/2658, H01Q3/2682, H01Q3/44 take precedence

Abstract

An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.

Claims

1. A packaging assembly for an integrated circuit, said assembly comprising:

a first semiconductor layer and a second semiconductor layer defining a first cavity therebetween;

a first sealing ring extending around the first cavity and sealing the first semiconductor layer to the second semiconductor layer so as to hermetically seal the first cavity; and

a plurality of circuit components electrically coupled together within the first cavity, wherein the first and second semiconductor layers are portions of semiconductor wafers on which the plurality of circuit components are fabricated.

2. The assembly according to claim 1 further comprising a patch antenna element deposited on an outside surface of the first semiconductor layer.

3. The assembly according to claim 1 further comprising a side radiating antenna element fabricated within the cavity.

4. The assembly according to claim 1 wherein the sealing ring is a conductive metal sealing ring.

5. The assembly according to claim 4 wherein the sealing ring is a combination of gold and indium.

6. The assembly according to claim 1 further comprising a third semiconductor layer and a second sealing ring, said third semiconductor layer and said second semiconductor layer defining a second cavity therebetween including electrical components of the circuit mounted therein, wherein the second sealing ring seals the third semiconductor layer to the second semiconductor layer so that the electrical components are hermetically sealed within the second cavity.

7. The assembly according to claim 1 wherein the first and second semiconductor layers are part of a plurality of semiconductor layers whose number is defined by the size of the components in the circuit.

8. The assembly according to claim 1 wherein the circuit is a transceiver circuit that is part of an antenna front end.

9. The assembly according to claim 8 wherein the side dimension of the first and second semiconductor layers are about one-half of the wavelength of a frequency band used by the transceiver circuit, and wherein the transceiver circuit provides about a ±

60°

scan angle.

10. The assembly according to claim 1 wherein the plurality of electrical components include power amplifiers, low noise amplifiers, phase shifters and digital controllers.

11. The assembly according to claim 1 wherein the semiconductor material of the first semiconductor layer is different than the semiconductor material of the second semiconductor layer.

12. The assembly according to claim 1 wherein the semiconductor material of the first and second semiconductor layers is selected from the group consisting of silicon, gallium arsenide and indium phosphide.

13. A packaging assembly for one or more integrated circuits, said assembly comprising:

a plurality of semiconductor layers; and

a plurality of circuit components fabricated on the semiconductor layers where circuit components are positioned within cavities between the semiconductor layers, said semiconductor layers being sealed together so that the circuit components within the cavities are hermetically isolated from the environment.

14. The assembly according to claim 13 further comprising an antenna element formed on an outside surface of one of the semiconductor layers.

15. The assembly according to claim 13 wherein the number of semiconductor layers is defined by the size of the components in the circuit, spacing between components in the circuit and a frequency band used by the circuit.

16. The assembly according to claim 13 wherein at least two of the plurality of semiconductor layers are made of different semiconductor materials.

17. A phased antenna array including a plurality of antennas and a plurality of transceiver circuits where a separate antenna is provided for each transceiver circuit, each transceiver circuit and antenna being part of an integrated packaging assembly, where each packaging assembly comprises:

a first semiconductor layer and a second semiconductor layer defining a first cavity therebetween;

a first sealing ring extending around the first cavity and sealing the first layer to the second layer so as to hermetically seal the first cavity; and

a plurality of circuit components electrically coupled together within the first cavity, said antenna being deposited on an outside surface of the first or second semiconductor layer, wherein the first and second semiconductor layers are portions of semiconductor wafers on which the plurality of circuit components are fabricated.

18. The antenna array according to claim 17 wherein the side dimension of the first and second semiconductor layers is about one-half the wavelength of the frequency band used by the transceiver circuit so as provide a scan angle of about ±

60°

.

19. The antenna array according to claim 17 wherein the first sealing ring is a conductive metal sealing ring.

20. The antenna array according to claim 19 wherein the first sealing ring is a combination of gold and indium.

21. The antenna array according to claim 17 further comprising a third semiconductor layer and a second sealing ring, said third semiconductor layer and said second semiconductor layer defining a second cavity therebetween including electrical components of the circuit mounted therein, wherein the second sealing ring seals the third semiconductor layer to the second semiconductor layer so that the electrical components are hermetically sealed within the second cavity.

22. The antenna array according to claim 17 wherein the plurality of electrical components include power amplifiers, low noise amplifiers, phase shifters and digital controllers.

23. The antenna array according to claim 17 wherein the semiconductor material of the first semiconductor layer is different than the semiconductor material of the second semiconductor layer.