Integrated circuit (IC) package stacking and IC packages formed by same

• US 20070290376A1
• Filed: 10/30/2006
• Published: 12/20/2007
• Est. Priority Date: 06/20/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhao, Sam Ziqun, Khan, Rezaur Rahman
• Granted Patent: US 8,581,381 B2
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92127 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92242 the first connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Methods, systems, and apparatuses for integrated circuit (IC) package vertical interconnection are described herein. In an aspect of the invention, an IC package includes an IC die with contact pads. The IC package also includes interconnect members which are coupled to the die at the contact pads. An encapsulating material encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. A second IC package is coupled to the first IC package through the plurality of interconnect members of the first IC package. In an example, solder balls attached to a bottom of the second IC package are coupled to the contact surfaces of the interconnect members to couple the first IC package and the second IC package.

Claims

1. An integrated circuit (IC) package, comprising:

an IC die having a plurality of contact pads;

a plurality of interconnect members coupled to the plurality of contact pads; and

an encapsulating material that encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material.

2. The IC package of claim 1, wherein each interconnect member is a truncated solder ball.

3. The IC package of claim 1, wherein the surface of the encapsulating material has a cavity in which the contact surface of each of the interconnect members is accessible.

4. The IC package of claim 1, further comprising:

a substrate having a first surface that mounts the IC die; and

a second plurality of interconnect members;

wherein the first surface of the substrate has a plurality of contact pads;

wherein the second plurality of interconnect members are each coupled to a corresponding contact pad of the plurality of contact pads on the first surface of the substrate;

wherein the second plurality of interconnect members are encapsulated by the encapsulating material such that a contact surface of each interconnect member of the second plurality of interconnect members is accessible at the surface of the encapsulating material.

5. The package of claim 1, wherein each interconnect member of the plurality of interconnect members comprises a metal.

6. The package of claim 5, wherein the metal is gold, copper, aluminum, silver, nickel, tin, or a metal alloy.

7. The package of claim 1, wherein each interconnect member of the plurality of interconnect members comprises a thermally conductive epoxy.

8. The package of claim 1, wherein each interconnect member of the plurality of interconnect members comprises a core material coated with a bonding material.

9. The package of claim 1, wherein each interconnect member of the plurality of interconnect members comprises a post.

10. A stacked integrated circuit (IC) packaging device, comprising:

A first IC package, comprising;

an IC die having a plurality of contact pads,

a plurality of interconnect members coupled to the plurality of contact pads, and

an encapsulating material that encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material; and

a second IC package coupled to the first IC package through the plurality of interconnect members of the first IC package.

11. The stacked integrated circuit (IC) packaging device of claim 10,

wherein the surface of the encapsulating material has a cavity in which the contact surface of each of the interconnect members is accessible,

wherein the second IC package is disposed at least partially in the cavity.

12. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member is a truncated solder ball.

13. The stacked integrated circuit (IC) packaging device of claim 10, wherein the first IC package further comprises:

a substrate having a first surface that mounts the IC die; and

a second plurality of interconnect members;

wherein the first surface of the substrate has a plurality of contact pads;

wherein the second plurality of interconnect members are each coupled to a corresponding contact pad of the plurality of contact pads on the first surface of the substrate;

wherein the second plurality of interconnect members are encapsulated by the encapsulating material such that a contact surface of each interconnect member of the second plurality of interconnect members is accessible at the surface of the encapsulating material.

wherein the second IC package is coupled to the first IC package through the second plurality of interconnect members.

14. The stacked integrated circuit (IC) packaging device of claim 10, wherein the second IC package further comprises a plurality of solder balls attached to a bottom surface of the second IC package;

wherein each solder ball of the plurality of solder balls is coupled to a corresponding contact surface of an interconnect member of the plurality of interconnect members.

15. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member of the plurality of interconnect members comprises a metal.

16. The stacked integrated circuit (IC) packaging device of claim 15, wherein the metal is gold, copper, aluminum, silver, nickel, tin, or a metal alloy.

17. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member of the plurality of interconnect members comprises a thermally conductive epoxy.

18. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member of the plurality of interconnect members comprises a core material coated with a bonding material.

19. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member of the plurality of interconnect members comprises a post.

20. A method of manufacturing an integrated circuit (IC) package, comprising:

(a) attaching an IC die to a first surface of a substrate, the die having a plurality of contact pads;

(b) coupling a plurality of interconnect members to the plurality of contact pads;

(c) coupling the die and the substrate with at least one wirebond;

(d) encapsulating the die and the plurality of interconnect members in an encapsulating material; and

(e) at least partially exposing the plurality of interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material.

21. The method of claim 20, further comprising the step of:

(f) mounting a plurality of solder balls to a second surface of the substrate.

22. The method of claim 20, wherein step (e) further comprising:

removing a layer of the encapsulating material.

23. The method of claim 20, wherein step (e) further comprising:

forming a cavity in the encapsulating material.

24. The method of claim 20, wherein step (c) is performed before step (b).

25. The method of claim 20, wherein step (b) is performed before step (c).

26. A method of manufacturing a stacked integrated circuit (IC) packaging device, comprising:

(a) manufacturing a first IC package, comprising;

(1) attaching an IC die to a first surface of a substrate, the die having a plurality of contact pads;

(2) coupling a plurality of interconnect members to the plurality of die contact pads;

(3) coupling the die and the substrate with at least one wire bond;

(4) encapsulating the die and interconnect members in an encapsulating material; and

,

(5) at least partially exposing the plurality of interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material;

(b) coupling a second IC package to the first IC package at the plurality of interconnect members of the first IC package.

27. The method of claim 26, wherein step (a) further comprises:

(6) mounting a plurality of solder balls to a second surface of the substrate.

28. The method of claim 26, wherein step (a)(5) further comprises:

removing a layer of the encapsulating material.

29. The method of claim 26, wherein step (a)(5) further comprising:

forming a cavity in the encapsulating material.

30. The method of claim 28, wherein step (a)(3) is performed before step (a)(2).

31. The method of claim 26, wherein step (a)(2) is performed before step (a)(3).

32. The method of claim 26, wherein the second IC package has a plurality of solder balls attached to a bottom surface of the second IC package, wherein step (b) comprises:

coupling each solder ball of the plurality of solder balls to a corresponding contact surface of an interconnect member of the plurality of interconnect members.

33. An integrated circuit (IC) package, comprising:

a substrate having a plurality of contact pads on a first surface;

an IC die mounted to the first surface of the substrate;

a plurality of interconnect members coupled to the plurality of contact pads; and

an encapsulating material that encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material.

34. The IC package of claim 33, wherein each interconnect member is a truncated solder ball.

35. The package of claim 33, wherein each interconnect member of the plurality of interconnect members comprises a metal.

36. The package of claim 35, wherein the metal is gold, copper, aluminum, silver, nickel, tin, or a metal alloy.

37. The package of claim 33, wherein each interconnect member of the plurality of interconnect members comprises a thermally conductive epoxy.

38. The package of claim 33, wherein each interconnect member of the plurality of interconnect members comprises a core material coated with a bonding material.

39. A method of manufacturing an integrated circuit (IC) package, comprising:

(a) attaching an IC die to a first surface of a substrate, the first surface of the substrate having a plurality of contact pads;

(b) coupling a plurality of interconnect members to the plurality of contact pads;

(c) coupling the die and the substrate with at least one wirebond;

(d) encapsulating the die and the plurality of interconnect members in an encapsulating material; and

(e) at least partially exposing the plurality of interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material.