Integrated circuit and method for writing information

• US 20070290706A1
• Filed: 12/27/2006
• Published: 12/20/2007
• Est. Priority Date: 06/02/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Granted Patent: US 8,207,823 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: H01L 21/67005 Apparatus not specifically provided for elsewhere processes per se H01L21/30, H01L21/46, H01L23/00; simple temporary support means, e.g. using adhesives, electric or magnetic means H01L21/68, H01L21/302
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit is provided. The integrated circuit includes an RFID tag configured to store various administrative information after testing at a wafer level in response to a radio frequency signal, and an interface unit configured to perform the function of an interface between the integrated circuit and the RFID tag for storing the information in the RFID tag. An antenna of the RFID tag is formed using a wire and a lead frame. A method for writing information of an integrated circuit is also provided. The method includes the steps of performing a wafer processing of an integrated circuit having a RFID tag; performing a wafer level test of the integrated circuit; transmitting and receiving a radio frequency signal to store various administrative information in the RFID tag; and storing a chip confirmation code in the RFID tag.

Claims

1. An integrated circuit comprising:

a Radio Frequency Identification (RFID) tag, the RFID tag being configured to store various administrative information, wherein information is stored in the RFID tag after testing at a wafer level by transmitting the information in response to a radio frequency signal.

2. The integrated circuit according to claim 1, further comprising:

an interface unit configured to perform the function of an interface between the integrated circuit and the RFID tag for storing the information in the RFID tag.

3. The integrated circuit according to claim 1, wherein the RFID tag includes an antenna formed with a wire and a lead frame.

4. The integrated circuit according to claim 1, wherein the integrated circuit is formed in an SOP (Small Outline Package) or an FBGA (Fine Pitch Ball Grid Array) form factor.

5. The integrated circuit according to claim 1, wherein the integrated circuit includes one of a DRAM, a flash memory, a FeRAM, a CPU, an SOC, an ASIC, and a solid state semiconductor.

6. The integrated circuit according to claim 1, wherein the RFID tag includes:

an analog block configured to receive a radio frequency signal to output an operation command signal;

a digital block configured to generate an address and an operation control signal in response to the operation command signal, and output a response signal corresponding to the operation command signal to the analog block; and

a memory block configured to receive the operation control signal to generate an internal control signal, store data in response to the internal control signal, and output the stored data.

7. The integrated circuit according to claim 6, wherein the memory block includes:

a word line decoder configured to decode the address to select a word line;

a control signal block configured to generate the internal control signal in response to the operation control signal;

a cell array configured to store the data; and

an input/output block configured to control data input/output between the cell array and a data bus in response to the internal control signal.

8. The integrated circuit according to claim 6, wherein the cell array includes:

a sense amplifier configured to sense and amplify the data in response to the internal control signal;

a bit line equalizing unit configured to precharge a bit line in response to a bit line equalizing signal; and

a memory array having a plurality of unit cells.

9. An integrated circuit comprising:

a Radio Frequency Identification (RFID) tag, the RFID tag being configured to store various administrative information, wherein information is stored in the RFID tag after testing a wafer level by transmitting the information in response to a radio frequency signal; and

an interface unit configured to perform the function of an interface between the integrated circuit and the RFID tag for storing the information in the RFID tag.

10. The integrated circuit according to claim 9, wherein the RFID tag includes an antenna formed using a wire and a lead frame.

11. The integrated circuit according to claim 10, wherein antenna pads are formed in a region on the RFID tag and in a region on the integrated circuit, the antenna pad being connected to the antenna.

12. The integrated circuit according to claim 9, wherein the integrated circuit is formed in an SOP (Small Outline Package) or an FBGA (Fine Pitch Ball Grid Array) form factor.

13. The integrated circuit according to claim 9, wherein the integrated circuit is one of a DRAM, a flash memory, a FeRAM, a CPU, an SOC, an ASIC, and a solid state semiconductor.

14. The integrated circuit according to claim 9, wherein the RFID tag includes:

an analog block configured to receive a radio frequency signal to output an operation command signal;

a digital block configured to generate an address and an operation control signal in response to the operation command signal, and output a response signal corresponding to the operation command signal to the analog block; and

a memory block configured to receive the operation control signal to generate an internal control signal, store data in response to the internal control signal and output the stored data.

15. The integrated circuit according to claim 14, wherein the memory block includes:

a word line decoder configured to decode the address to select a word line;

a control signal block configured to generate the internal control signal in response to the operation control signal;

a cell array configured to store the data; and

an input/output block configured to control data input/output between the cell array and a data bus in response to the internal control signal.

16. The integrated circuit according to claim 15, wherein the cell array includes:

a sense amplifier configured to sense and amplify the data in response to the internal control signal;

a bit line equalizing unit configured to precharge a bit line in response to a bit line equalizing signal; and

a memory array having a plurality of unit cells.

17. A method for writing information of an integrated circuit, the method comprising the steps of:

performing a wafer processing of an integrated circuit, the integrated circuit having a Radio Frequency Identification (RFID) tag;

performing a wafer level test of the integrated circuit; and

transmitting and receiving a radio frequency signal to store various administrative information in the RFID tag.

18. The method according to claim 17, further comprising storing a chip confirmation code in the RFID tag.

19. The method according to claim 18, wherein the chip confirmation code is stored by an interface between the integrated circuit and the RFID tag.

20. The method according to claim 17, wherein the integrated circuit includes one of a DRAM, a flash memory, a FeRAM, a CPU, an SOC, an ASIC, and a solid state semiconductor chip.