Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay

• US 20070290735A1
• Filed: 06/15/2006
• Published: 12/20/2007
• Est. Priority Date: 06/15/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ali, Shahid, Balasubramanian, Satheesh, Manobar, Sujan
• Granted Patent: US 7,511,552 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

Claims

1. A system, comprising:

a first circuit to operate based on a first voltage of a first power supply;

a second circuit to operate based on a second voltage of a second power supply;

a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply;

a first set of sequentially coupled pull-up and pull-down sub-circuits of the level shifter circuit cross coupled to a second set of sequentially coupled pull-up and pull-down sub-circuits of the level shifter circuit to generate a positive feedback loop;

an output node of the level shifter circuit coupled to a common node between the pull-up and the pull-down sub-circuits of the first set of sequentially coupled pull-up and pull-down sub-circuits through an output inverter;

a pull-up NMOS transistor having a gate contact coupled to an input of the second set of pull-up and pull-down sub-circuits, a source contact coupled to an input of the output inverter and a drain contact coupled to the second voltage of the level shifter circuit; and

a pull-down NMOS transistor having a gate contact coupled to the input of the second set of pull-up and pull-down sub-circuits, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

2. The system of claim 1 wherein the system has reduced delays of a falling path of a signal and a rising path of the signal as compared to those of a conventional level shifter circuit.

3. The system of claim 2 in which delays of the falling path of the signal and the rising path of the signal are substantially close.

4. The system of claim 3 in which delays of both the falling path and the rising path of the signal of the level shifter circuit is substantially close to that of two logic stages.

5. The system of claim 4 wherein the system has an increased speed of operation due to reduced delays in the falling path and the rising path of the signal of the level shifter circuit.

6. The system of claim 5 wherein the system has a reduced power dissipation due to reduced delays of both the falling and the rising path of the signal of the level shifter circuit.

7. The system of claim 6 wherein the system has a reduced duty cycle distortion caused by an insertion of the level shifter circuit by making delays of both the falling path and the rising path substantially close.

8. The system of claim 7 in which a duty cycle is maintained approximately 50% throughout the system by making delays of both the falling path and the rising path substantially close.

9. The system of claim 1 wherein the system has a reduced area of an integrated circuit due to a reduced size of a P-well of the level shifter circuit which has a smaller number of PMOS transistors as compared to a conventional level shifter circuit.

10. The system of claim 1 wherein the system operates at a broader range of temperatures between −

15 degrees C. and 65 degrees C., and wherein the voltages and process variations in which the level shifter circuit operates without failure improves through the output node, the pull-up NMOS transistor, and the pull down NMOS transistor.

11. A level shifter circuit, comprising:

a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially coupled pull-up and pull-down sub-circuit to generate a positive feedback loop;

an input node of the first set coupled to an input node of the level shifter;

an input node of the second set coupled to a inverse logic of the input node of the level shifter; and

an output node coupled to a shared node between the pull-up and pull-down sub-circuits of the first set through an output inverter.

12. The level shifter circuit of claim 11 wherein the level shifter circuit has a reduced delay of a rising path of a signal of the level shifter circuit because of a placement of the output node coupled to the shared node between the pull-up and pull-down sub-circuits of the first set through the output inverter.

13. The system of claim 12 wherein a rise path delay of the level shifter circuit is reduced by at least 50% because of the output node coupled to the shared node between the pull-up and pull-down sub-circuits of the first set through the output inverter.

14. A level shifter circuit, comprising:

a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially coupled pull-up and pull-down sub-circuits to generate a positive feedback loop;

an input node of the first set of sequentially coupled pull-up and pull-down sub-circuits coupled to an input node of the level shifter;

an input node of the second set of sequentially coupled pull-up and pull-down sub-circuits coupled to a logical inverse of the input node of the level shifter;

an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter;

a pull-up NMOS transistor with a gate contact coupled to the input of the second set of pull-up and pull-down sub-circuits, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and

a pull-down NMOS transistor with a gate contact coupled to the input of the second set of pull-up and pull-down sub-circuits, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

15. The level shifter circuit of claim 14 wherein the level shifter circuit has reduced delays of a falling path of a signal and a rising path of the signal as compared to those of a conventional level shifter circuit.

16. The level shifter circuit of claim 15 in which delays of the falling path of the signal and the rising path of the signal are substantially close to each other.

17. The level shifter circuit of claim 16 in which delays of both the falling path and the rising path of the level shifter circuit is substantially close to that of two logic stages.

18. The level shifter circuit of claim 17 in which a speed of operation is increased due to reduced delays in the falling path and the rising path of a signal of the level shifter circuit because of the output node, the pull-up NMOS transistor, and the pull down NMOS transistor.

19. The level shifter circuit of claim 16 in which a duty cycle distortion of the level shifter is reduced by making delays of both the falling path and the rising path substantially close.

20. The level shifter circuit of claim 19 in which a duty cycle is maintained approximately 50% through out the system by making delays of both the falling path and the rising path substantially close.

21. The level shifter circuit of claim 14 in which an area of the level shifter circuit is reduced due to reduced size of a P-well of the level shifter circuit which has a smaller number of PMOS transistors as compared to a conventional level shifter circuit.

22. The system of claim 14 wherein the level shifter circuit operates at a broader range of temperatures between −

15 degrees C. and 65 degrees C., and wherein the voltages and process variations in which the level shifter circuit operates without failure improves through the output node, the pull-up NMOS transistor, and the pull down NMOS transistor.

23. A method, comprising:

generating a positive feedback loop through a cross-coupling of a first set of sequentially coupled pull-up and pull-down sub-circuits to a second set of sequentially coupled pull-up and pull-down sub-circuits;

coupling a first set input node of the first set of sequentially coupled pull-up and pull-down sub-circuits to a level shifter input node;

coupling a second set input node of the second set of sequentially coupled pull-up and pull-down sub-circuits to a inverse logic of the level shifter input node;

coupling a level shifter output node to a shared node between a first pull-up sub-circuit and a first pull-down sub-circuit of the first set of sequentially coupled pull-up and pull-down sub-circuits through an output inverter;

placing a pull-up NMOS transistor having a gate contact coupled to the second set input node of the second set of pull-up and pull-down sub-circuits, a source contact coupled to an output inverter input node and a drain contact coupled to a level shifter output voltage; and

placing a pull-down NMOS transistor with a gate contact coupled to the second set input node of the second set of pull-up and pull-down sub-circuits, a drain contact coupled to an output inverter output node and a source contact coupled to a ground.

24. A method of claim 23 further comprising placing a serially coupled pair of PMOS transistors in the first set of sequentially coupled pull-up and pull-down subcicuits and the second set of sequentially coupled pull-up and pull-down sub-circuit.

25. A method of design of an integrated circuit, comprising:

reducing a rise path delay of the integrated circuit through a level shifter circuit design having a an output node coupled to a logical inverse of a shared node between a first pull-up sub-circuit and a first pull-down sub-circuit of the first set of sequentially coupled pull-up and pull-down sub-circuits which is cross coupled to a second set of sequentially coupled pull-up and pull-down sub-circuits circuits; and

reducing a fall path delay of the integrated circuit through a reduction in a capacitive discharge time of the output node of the level shifter circuit and a reduction in a capacitive charge time of the shared node between the first pull-up sub-circuit and the first pull-down sub-circuit of the first set of sequentially coupled pull-up and pull-down sub-circuits through a placement of a pull-down NMOS transistor and a pull-up NMOS transistor in a fall path of the level shifter circuit.

26. The method of claim 25 further comprising providing a design scheme to make a delay of a fall path and a delay of a rise path substantially close.

27. The method of claim 26 further comprising providing a design scheme to ensure that the level shifter circuit operates without failures for broader ranges of temperatures and voltages as well as for broader variations in fabrication processes.