Method and Apparatus for Universally Decoding Commands of a Remote Controller

• US 20070290880A1
• Filed: 09/03/2006
• Published: 12/20/2007
• Est. Priority Date: 06/07/2006
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Lin, Sheng-Feng
• Granted Patent: US 8,072,315 B2
• Time in Patent Office: Days
• US Class Current: 340/12.18
• CPC Class Codes: G08C 17/00 Arrangements for transmitting signals characterised by the use of a wireless electrical link
• CPC Class Codes: G08C 2201/20 Binding and programming of remote control devices

Abstract

A universal decoding device and associated method is provided. The universal decoding device includes a counter unit for counting signal cycles and a logic unit for identifying coded data or commands according to counted signal cycles. The logic unit includes a register, an boundary logic unit, a key identification unit, a code bank, a multiplexer, and a FIFO memory. The universal decoding device is capable of operating in a full decoding mode, a raw data decoding mode, and a software decoding mode. In the full decoding mode, the FIFO stores remote control commands corresponding to the counted signal cycles through the multiplexer. In the raw data decoding mode, the FIFO stores raw data corresponding to the counted signal cycles through the multiplexer. In the software decoding mode, the FIFO stores the counted signal cycles provided by the counter unit through the multiplexer.

Claims

1. A method of universally decoding a remote control command comprising:

receiving a remote control signal;

counting a plurality of numbers of signal cycles traversing between a plurality of adjacent edges in the remote control signal; and

identifying a plurality of coded data based on the numbers of signal cycles.

2. The method of claim 1 further comprising suppressing electromagnetic glitch interference in the remote control signal.

3. The method of claim 1 further comprising identifying the remote control command represented by the remote control signal based on a combination of the coded data.

4. The method of claim 1, wherein said identifying step substantially identifies one of the numbers of signal cycles as a logic coded data corresponding to the first value when the number of signal cycles is greater than a difference of the first value and a first threshold value and the number of signal cycles is less than a sum of the first value and a second threshold.

5. The method of claim 4, wherein the first threshold is substantially equal to the second threshold.

6. The method of claim 1, wherein the adjacent edges include a falling edge and a rising edge.

7. A universal decoding apparatus used in a universal remote control receiver comprising:

a counter unit for receiving a remote control signal and counting a plurality of numbers of signal cycles traversing between a plurality of adjacent edges in the remote control signal; and

a logic unit for identifying a plurality of coded data corresponding to the numbers of signal cycles.

8. The universal decoding apparatus of claim 7 further comprising a noise suppression unit coupled to a front end of the counter unit for suppressing an electromagnetic glitch interference in the remote control signal.

9. The universal decoding apparatus of claim 7, wherein the logic unit comprises:

a key identification unit for identifying the coded data based on the numbers of signal cycles; and

a code bank coupled to the key identification unit for storing the coded data.

10. The universal decoding apparatus of claim 9, wherein the key identification unit identifies a remote control command represented by the remote control signal based on a combination of the coded data.

11. The universal decoding apparatus of claim 7, wherein the logic unit comprises:

a register for storing and setting a first threshold and a second threshold; and

a boundary logic detector coupled to the register for identifying one of the numbers of signal cycles as a logic coded data corresponding to a first value when the number signal cycles is greater than a difference between the first value and the first threshold and less than a sum of the first value and the second threshold.

12. The universal decoding apparatus of claim 11, wherein the first threshold is substantially equal to the second threshold.

13. The universal decoding apparatus of claim 7, wherein the adjacent edges include a falling edge and a rising edge.

14. The universal decoding apparatus of claim 7 further comprising a first-in-first-out (FIFO) memory for storing the coded data and the counter unit can issue an interrupt to the microprocessor for reading the coded data.

15. The universal decoding apparatus of claim 7, wherein the logic unit comprises:

a register for storing a first threshold and a second threshold;

a boundary logic detector coupled to the register for identifying one of the numbers of signal cycles as a logic coded data corresponding to a first value when the number of signal cycles is greater than a difference between the first value and the first threshold and less than a sum of the first value and the second threshold;

a key identification unit coupled to the boundary logic detector for identifying the coded data; and

a code bank coupled to the key identification unit for storing the coded data.

16. The universal decoding apparatus of claim 15, wherein the identification unit identifies a command represented by the remote control signal based on a combination of the plurality of coded data, and stores the command in the code bank.

17. The universal decoding apparatus of claim 16 further comprising a first-in-first-out (FIFO) memory coupled to the code bank for storing the coded data and the counter unit can issue an interrupt to the microprocessor for reading the coded data.

18. The universal decoding apparatus of claim 15 further comprising:

a multiplexer coupled to the code bank and the counter unit; and

a first-in-first-out (FIFO) memory coupled to the multiplexer.

19. The universal decoding apparatus of claim 18, wherein the universal decoding apparatus can operate in a full decode mode, a raw data mode, and a software decode mode.

20. The universal decoding apparatus of claim 19, wherein when operating in the full decode mode, the FIFO memory stores a command based on the numbers of signal cycles through the multiplexer.

21. The universal decoding apparatus of claim 19, wherein when operating in the raw data mode, the FIFO memory stores raw data based on the numbers of signal cycles through the multiplexer.

22. The universal decoding apparatus of claim 19, wherein when operating in the software decode mode, the FIFO memory directly stores the numbers of signal cycles from the counter unit through the multiplexer.