Two-Wire Connection to a Key Matrix in a Mobile Device

• US 20070290889A1
• Filed: 02/28/2007
• Published: 12/20/2007
• Est. Priority Date: 06/20/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wiley, George Alan
• Granted Patent: US 8,471,733 B2
• Time in Patent Office: Days
• US Class Current: 341/22
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence
• CPC Class Codes: H03M 11/24 using analogue means , e.g. by coding the states of multiple switches into a single multi-level analogue signal or by indicating the type of a device using the voltage level at a specific tap of a resistive divider

Abstract

A first current is driven through a first current path from a first common node, through a key matrix, and to a second common node when a key is pressed. A first measurement of the first current path resistance is made. A second current is then driven through a second current path from the second common node, through the key matrix, and to the first common node. A second measurement of the second current path resistance is made. The first and second measurements are used to identify the key that was pressed. Each key corresponds to a unique pair of first and second measurement values. In one example, non-linear resistance circuits are disposed at the ends of the row and column conductors of the key matrix such that a row resistor in the first current path is measured independently of a column resistor in the second current path.

Claims

1. A circuit comprising:

a first common node;

a first resistor having a first lead and a second lead, the first lead being coupled to the first common node;

a second resistor having a first lead and a second lead, the first lead being coupled to the first common node;

a second common node;

a third resistor having a first lead and a second lead, the first lead being coupled to the second common node;

a fourth resistor having a first lead and a second lead, the first lead being coupled to the second common node;

a key matrix having a first conductor, a second conductor, a third conductor, a fourth conductor, a first key, a second key, a third key and a fourth key, wherein the first conductor is coupled to the second lead of the first resistor, wherein the second conductor is coupled to the second lead of the second resistor, wherein the third conductor is coupled to the second lead of the third resistor, wherein the fourth conductor is coupled to the second lead of the fourth resistor, wherein a pressing of the first key causes the first conductor to be coupled to the third conductor, wherein a pressing of the second key causes the first conductor to be coupled to the fourth conductor, wherein a pressing of the third key causes the second conductor to be coupled to the third conductor, and wherein the pressing of the fourth key causes the second conductor to be coupled to the fourth conductor;

a first diode having a first lead a second lead, the first lead being coupled to the first lead of the first resistor, the second lead being coupled to the second lead of the first resistor; and

a second diode having a first lead a second lead, the first lead being coupled to the first lead of the second resistor, the second lead being coupled to the second lead of the second resistor.

2. The circuit of claim 1, further comprising:

a third diode having a first lead a second lead, the first lead being coupled to the first lead of the third resistor, the second lead being coupled to the second lead of the third resistor; and

a fourth diode having a first lead a second lead, the first lead being coupled to the first lead of the fourth resistor, the second lead being coupled to the second lead of the fourth resistor.

3. The circuit of claim 1, wherein the first resistor has a resistance R1, wherein the second resistor has a resistance R2, wherein the third resistor has a resistance R3, and wherein the fourth resistor has a resistance R4, wherein R3 and R4 are substantially different resistances, wherein R1 is greater than R3, wherein R1 is greater than R4, wherein R2 minus R1 is greater than R3, and wherein R2 minus R1 is greater than R4.

4. The circuit of claim 2, wherein the first resistor has a resistance R1, wherein the second resistor has a resistance R2, wherein the third resistor has a resistance R3, and wherein the fourth resistor has a resistance R4, wherein R2 is greater than R1, wherein R2 is greater than R3, wherein R4 is greater than R1, and wherein R4 is greater than R3.

5. The circuit of claim 1, further comprising:

an integrated circuit that drives a first current from the first common node to the second common node, and also drives a second current from the second common node to the first common node.

6. The circuit of claim 1, wherein the key matrix comprises more than thirty keys, wherein the pressing of any single key of the thirty keys causes a current path to exist through the key matrix from the first common node to the second common node if the first common node has a first voltage polarity with respect to the second common node.

7. The circuit of claim 1, wherein the key matrix comprises more than thirty keys, wherein the pressing of a key of the thirty keys causes a first current path to exist through the key matrix from the first common node to the second common node if the first common node has a first voltage polarity with respect to the second common node, wherein the first current path has a first resistance, and wherein the pressing of the key also causes a second current path to exist through the key matrix from the second common node to the first common node if the first common node has a second voltage polarity with respect to the second common node, wherein the second current path has a second resistance that is different from the first resistance.

8. The circuit of claim 1, wherein the key matrix includes more than thirty keys, the circuit further comprising:

means for determining which key of the key matrix was pressed if a single key was pressed, wherein the means drives a first current from the first common node to the second common node and also drives a second current from the second common node to the first common node.

9. The circuit of claim 8, wherein the means is also for differentiating a situation in which two of the keys is pressed from a situation in which a single key is pressed.

10. The circuit of claim 2, wherein the key matrix includes more than thirty keys, the circuit further comprising:

means for determining which key of the key matrix was pressed if a single key was pressed, wherein the means drives a first current from the first common node to the second common node and also drives a second current from the second common node to the first common node.

11. The circuit of claim 10, wherein the means is also for differentiating a situation in which two of the keys is pressed from a situation in which a single key is pressed.

12. The circuit of claim 1, further comprising:

a fifth resistor having a first lead and a second lead, the first lead being coupled to the first common node, and second resistor being coupled to the second common node.

13. The circuit of claim 1, wherein the key matrix includes more than thirty keys, and wherein the first resistor, second resistor, third resistor, fourth resistor, first diode and second diode are integrated onto a single integrated circuit.

14. The circuit of claim 2, wherein the key matrix includes more than thirty keys, and wherein the first resistor, second resistor, third resistor, fourth resistor, first diode, second diode, third diode and fourth diode are integrated onto a single integrated circuit.

15. A method comprising:

(a) driving a first current through a first current path from a first common node, through a key matrix, and to a second common node, wherein the first current flows through the first current path when one of a plurality of keys of the key matrix is pressed;

(b) making a first measurement of an electrical characteristic during the flow of the first current in (a);

(c) driving a second current through a second current path from the second common node, through the key matrix, and to the first common node, wherein the second current flows through the second current path when said one key is pressed;

(d) making a second measurement of an electrical characteristic during the flow of the second current in (c); and

(e) using the first and second measurements to identify said one key.

16. The method of claim 15, wherein the first current path has a first resistance between the first common node and the second common node, wherein second current path has a second resistance between the first common node and the second common node, and wherein the first resistance is substantially different than the second resistance.

17. The method of claim 15, wherein the first current flows principally through a resistor and not through a diode, a first lead of the resistor being coupled to a first lead of the diode, a second lead of the resistor being coupled to a second lead of the diode, and wherein the second current flows principally through the diode and not through the resistor.

18. The method of claim 15, wherein the key matrix includes more than thirty keys.

19. The method of claim 15, wherein the electrical characteristic is taken from the group consisting of:

a resistance between the first common node and the second common node, a voltage between the first common node and the second common node, and a current flowing between the first common node and the second common node.

20. The method of claim 15, wherein an integrated circuit drives the first current in (a), drives the second current in (c), and identifies said one key in (e).

21. The method of claim 15, wherein the first current flows principally through a resistor and not through a transistor, a first lead of the resistor being coupled to a first lead of the transistor, a second lead of the resistor being coupled to a second lead of the transistor, and wherein the second current flows principally through the transistor and not through the resistor, wherein the transistor is controlled to be substantially nonconductive when the first current flows in (a), and wherein the transistor is controlled to be substantially conductive when the second current flows in (c).

22. The method of claim 15, further comprising:

(f) driving a third current from the first common node, through the key matrix, and to the second common node, making a third measurement of an electrical characteristic during the flow of the third current, and using the third measurement to determine that more than one key of the key matrix has been pressed simultaneously.

23. A circuit comprising:

a first common node;

a first resistor having a first lead and a second lead, the first lead being coupled to the first common node;

a second resistor having a first lead and a second lead, the first lead being coupled to the first common node;

a second common node;

a third resistor having a first lead and a second lead, the first lead being coupled to the second common node;

a fourth resistor having a first lead and a second lead, the first lead being coupled to the second common node;

a key matrix having a first conductor, a second conductor, a third conductor, a fourth conductor, a first key, a second key, a third key and a fourth key, wherein the first conductor is coupled to the second lead of the first resistor, wherein the second conductor is coupled to the second lead of the second resistor, wherein the third conductor is coupled to the second lead of the third resistor, wherein the fourth conductor is coupled to the second lead of the fourth resistor, wherein a pressing of the first key causes the first conductor to be coupled to the third conductor, wherein a pressing of the second key causes the first conductor to be coupled to the fourth conductor, wherein a pressing of the third key causes the second conductor to be coupled to the third conductor, and wherein the pressing of the fourth key causes the second conductor to be coupled to the fourth conductor;

a first transistor having a first lead a second lead, the first lead being coupled to the first lead of the first resistor, the second lead being coupled to the second lead of the first resistor; and

a second transistor having a first lead a second lead, the first lead being coupled to the first lead of the second resistor, the second lead being coupled to the second lead of the second resistor.

24. The circuit of claim 23, further comprising:

a third transistor having a first lead and a second lead, the first lead being coupled to the first lead of the third resistor, the second lead being coupled to the second lead of the third resistor; and

a fourth transistor having a first lead a second lead, the first lead being coupled to the first lead of the fourth resistor, the second lead being coupled to the second lead of the fourth resistor.

25. The circuit of claim 23, wherein the first transistor has a control input lead, wherein the second transistor has a control input lead, wherein the control input leads of the first and second transistors are coupled together and are also coupled to the second common node.

26. The circuit of claim 24, wherein the first transistor has a control input lead, wherein the second transistor has a control input lead, wherein the control input leads of the first and second transistors are coupled together and are also coupled to the second common node, wherein the third transistor has a control input lead, wherein the fourth transistor has a control input lead, wherein the control input leads of the third and fourth transistors are coupled together and are also coupled to the first common node.

27. The circuit of claim 23, wherein the first resistor has a resistance R1, wherein the second resistor has a resistance R2, wherein the third resistor has a resistance R3, and wherein the fourth resistor has a resistance R4, wherein R3 and R4 and substantially different resistances, wherein R1 is greater than both R3 and R4, wherein R2 minus R1 is greater than R3, and wherein R2 minus R1 is greater than R4.

28. The circuit of claim 24, wherein the first resistor has a resistance R1, wherein the second resistor has a resistance R2, wherein the third resistor has a resistance R3, and wherein the fourth resistor has a resistance R4, wherein R2 is greater than R1, wherein R2 is greater than R3, wherein R4 is greater than R1, and wherein R4 is greater than R3.

29. The circuit of claim 23, wherein the key matrix comprises more than thirty keys, wherein when any single key of the thirty keys is pressed both a first current path and a second current path are made to extend through the key matrix at different times between the first common node and the second common node.

30. The circuit of claim 29, further comprising:

an integrated circuit that controls the first and second transistors, that causes a first current to flow in the first current path, and that causes a second current to flow in the second current path.

31. The circuit of claim 23, further comprising:

a circuitry that determines the identity of a key that is pressed if a single key is pressed, and that can distinguish a situation in which two keys are pressed from a situation in which a single key is pressed.

32. An integrated circuit comprising:

a two-wire key matrix interface adapted to drive a first current through a non-linear resistance circuit of a key matrix during a key press event when the non-linear resistance circuit has a first resistance, and wherein the two-wire key matrix interface is also adapted to drive a second current through the non-linear resistance circuit of the key matrix during the key press event when the non-linear resistance circuit has a second resistance.

33. The integrated circuit of claim 32, wherein the two-wire key matrix interface comprises a first terminal and a second terminal, wherein the two-wire key matrix interface is adapted to drive the first current out of the first terminal and to receive the first current into the second terminal, and wherein the two-wire key matrix interface is adapted to drive the second current out of the second terminal and to receive the second current into the first terminal.

34. The integrated circuit of claim 32, wherein the two-wire key matrix interface comprises a first terminal and a second terminal, wherein the two-wire key matrix interface is adapted to drive the first current out of the first terminal and to receive the first current into the second terminal, and wherein the two-wire key matrix interface is adapted to drive the second current out of the first terminal and to receive the second current into the second terminal.

35. The integrated circuit of claim 32, wherein the first current has a first frequency, and wherein the second current has a second frequency.

36. The integrated circuit of claim 32, wherein the integrated circuit determines which one of a plurality of keys of the key matrix is pressed during the key press event.

37. The integrated circuit of claim 36, wherein the non-linear resistance circuit comprises:

a resistor having a first lead and a second lead; and

a diode having a first lead and a second lead, wherein the first lead of the diode is coupled to the first lead of the resistor, and wherein the second lead of the diode is coupled to the second lead of the resistor.

38. The integrated circuit of claim 36, wherein the non-linear resistance circuit comprises:

a resistor having a first lead and a second lead; and

a transistor having a source and a drain, wherein the source of the transistor is coupled to the first lead of the resistor, and wherein the drain of the transistor is coupled to the second lead of the resistor.