Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity

• US 20070291532A1
• Filed: 08/08/2007
• Published: 12/20/2007
• Est. Priority Date: 02/23/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tsuji, Takaharu
• Granted Patent: US 7,486,547 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Claims

1. A semiconductor wafer comprising:

a plurality of semiconductor chips arranged in rows and columns, the semiconductor chips each including a logic circuit for performing a predetermined processing on received data, and a plurality of magnetic memories integrated with said logic circuit on a common semiconductor chip, for storing at least data to be used by said logic circuit, each magnetic memory having a plurality of magnetic memory cells arranged in rows and columns, each magnetic memory cell including a magneto-resistance element formed of a fixed layer having a magnetization direction fixed independently of storage data, a free layer having a magnetization direction set according to the storage data, and a non-magnetic layer arranged between the fixed and free layers, the fixed layers in said plurality of magnetic memories being the same in magnetization direction, and said plurality of magnetic memories including first magnetic memories each having a common relationship of parallelism and anti-parallelism in magnetization direction between the free and fixed layers for a logical level of write data into each first magnetic memory, the fixed layers in said plurality of semiconductor chips being the same in magnetization direction, wherein

each of the magnetic memories includes a plurality of write current lines each for transmitting a current in a direction changed according to a logical level of write data, and for writing the write data into a memory cell through utilization of a magnetic field induced by the current transmitted through said each write current line, and

said plurality of magnetic memories each include an interface circuit to be individually accessed by said logic circuit through each respective interface circuit, and said first magnetic memories include magnetic memories having layouts arranged symmetrical with respect to an axis parallel to a direction of the write current line, the symmetrical layout including a layout of the interface circuit and a layout of a memory circuit including the plurality of magnetic memory cells.