Multi-chip switch based on proximity communication

• US 20070291535A1
• Filed: 06/14/2006
• Published: 12/20/2007
• Est. Priority Date: 06/14/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Eberle, Hans, Gura, Nils, Olesinski, Wladyslaw
• Granted Patent: US 7,490,189 B2
• Time in Patent Office: Days
• US Class Current: 365/174
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing

Abstract

A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a plurality of switching elements in accordance with a set of control signals, which correspond to a configuration of the switch. During this process, a plurality of proximity connectors, proximate to a surface of the semiconductor die, are configured to communicate the signals by capacitive coupling.

Claims

1. A switch containing a first semiconductor die having a surface, wherein the first semiconductor die comprises:

a plurality of proximity connectors proximate to the surface, wherein the first semiconductor die is configured to communicate signals by capacitive coupling using one or more of the plurality of proximity connectors;

a plurality of input ports configured to receive the signals;

a plurality of output ports configured to output the signals; and

a plurality of switching elements configured to selectively couple the plurality of input ports to the plurality of output ports in accordance with a set of control signals, wherein the set of control signals corresponds to a configuration of the switch.

2. The switch of claim 1, further comprising control logic coupled to the plurality of switching elements, wherein the control logic is configured to provide the set of control signals.

3. The switch of claim 1, further comprising one or more additional semiconductor dies coupled to the first semiconductor die, wherein the first semiconductor die and the one or more additional semiconductor dies are configured to communicate to one another by capacitive coupling using one or more of the plurality of proximity connectors.

4. The switch of claim 3, further comprising a bridge chip, wherein the bridge chip couples the first semiconductor die and at least one of the one or more additional semiconductor dies.

5. The switch of claim 4, wherein communication of at least a subset of the signals over the bridge chip is synchronous.

6. The switch of claim 4, wherein communication of at least a subset of the signals over the bridge chip is asynchronous.

7. The switch of claim 4, wherein the bridge chip includes a plurality of signal lines, and wherein the switch further comprises a circuit to resynchronize phases of respective signals on at least two signal lines in the plurality of signal lines.

8. The switch of claim 3, wherein the first semiconductor die and at least one of the one or more additional semiconductor dies have a common architecture.

9. The switch of claim 3, wherein the first semiconductor die and the one or more additional semiconductor dies are arranged in a linear array.

10. The switch of claim 3, wherein the first semiconductor die and the one or more additional semiconductor dies are arranged in a ring topology.

11. The switch of claim 3, wherein the first semiconductor die and the one or more additional semiconductor dies are arranged in a 2-dimensional array.

12. The switch of claim 3, wherein a communication bandwidth between the first semiconductor die and one of the one or more additional semiconductor dies approximately equals a total bandwidth associated with the signals received by the switch.

13. The switch of claim 1, wherein the switch includes a fat-tree network.

14. The switch of claim 1, wherein the switch includes a Clos network.

15. The switch of claim 1, further comprising an optical transceiver coupled to the first semiconductor die.

16. The switch of claim 1, wherein the first semiconductor die further comprises a memory.

17. The switch of claim 1, further comprising a demultiplexer coupled between the plurality of input ports and the plurality of switching elements, wherein the demultiplexer is configured to provide data units to the plurality of switching elements in accordance with the configuration of the switch.

18. The switch of claim 17, wherein a given data unit has a fixed size.

19. The switch of claim 17, wherein a given data unit has a variable size.

20. The switch of claim 17, further comprising a multiplexer coupled between the plurality of switching elements and the plurality of output ports, wherein the multiplexer is configured to receive data units from the plurality of switching elements.

21. The switch of claim 20, wherein the data units are received at the multiplexer in a different order than that provided by the demultiplexer.

22. The switch of claim 1, wherein the signals are encoded with a channel code that is DC-balanced.

23. A computer system, comprising:

a processor;

a memory; and

a switch containing a first semiconductor die having a surface, wherein the first semiconductor die comprises;

a plurality of proximity connectors proximate to the surface, wherein the first semiconductor die is configured to communicate signals by capacitive coupling using one or more of the plurality of proximity connectors;

a plurality of input ports configured to receive the signals;

a plurality of output ports configured to output the signals; and

a plurality of switching elements configured to selectively couple the plurality of input ports to the plurality of output ports in accordance with a set of control signals, wherein the set of control signals corresponds to a configuration of the switch.

24. A method for switching signals, comprising:

selectively coupling the signals from one or more input ports to one or more output ports of a switch in accordance with a switching configuration of the switch; and

while coupling the signals, communicating the signals between semiconductor dies in the switch using proximity connectors that are capacitively coupled.