Increasing the battery life of a mobile computing system in a reduced power state through memory compression

• US 20070291571A1
• Filed: 06/08/2006
• Published: 12/20/2007
• Est. Priority Date: 06/08/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Balasundaram, Sai P.
• Application Number:
  US11/450,214
• Publication Number:
  US 20070291571A1
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for increasing the battery life of a mobile computing system through memory compression. In some embodiments, an integrated circuit includes compression logic to compress at least a portion of the data in volatile memory independent of an operating system. The compression logic may compress the data responsive to an indication to transition to a reduced power state.

Claims

1. An integrated circuit comprising:

an input/output port to interface with volatile memory; and

compression logic coupled with the input/output port, the compression logic to compress at least a portion of the contents of volatile memory independent of an operating system.

2. The integrated circuit of claim 1, wherein the compression logic is to compress at least a portion of the contents in volatile memory responsive to an indication to transition to a reduced power state.

3. The integrated circuit of claim 2, wherein the indication to transition to the reduced power state comprises:

a command to transition to a suspend to random access memory (RAM) state.

4. The integrated circuit of claim 2, wherein the compression logic further comprises:

a timer to indicate when a threshold period of time has elapsed after receiving the indication to transition to the reduced power state.

5. The integrated circuit of claim 2, wherein the compression logic further comprises:

a first buffer to store a block of data read from volatile memory.

6. The integrated circuit of claim 5, wherein the compression logic further comprises:

a second buffer to store a compressed block of data to be written to volatile memory.

7. The integrated circuit of claim 2, wherein the compression logic includes logic to individually set a power state for each memory device in volatile memory.

8. The integrated circuit of claim 2, wherein the compression logic further comprises:

a read pointer to reference a block of uncompressed data; and

a write pointer to reference a block of compressed data.

9. The integrated circuit of claim 1, wherein the integrated circuit comprises a memory controller.

10. A method comprising:

receiving an indication to transition to a reduced power state; and

compressing at least a portion of data stored in a memory array responsive to receiving the indication to transition to the reduced power state.

11. The method of claim 10, wherein receiving the indication to transition to the reduced power state comprises:

receiving a suspend to random access memory (RAM) command.

12. The method of claim 10, wherein compressing at least a portion of the data stored in the memory array responsive to receiving the indication to transition to the reduced power state comprises:

compressing at least a portion of data stored in the memory array independent of an operating system.

13. The method of claim 12, further comprising:

determining whether a threshold period of time has elapsed.

14. The method of claim 13, wherein compressing at least a portion of the data stored in the memory array comprises:

compressing at least a portion of the data stored in the memory array if the threshold period of time has elapsed.

15. The method of claim 12, wherein compressing at least a portion of the data stored in the memory array independent of the operating system comprises:

reading a next block of data from volatile memory;

compressing the next block of data to create a compressed block of data; and

writing the compressed block of data to volatile memory.

16. The method of claim 10, further comprising:

transitioning to a reduced power state subsequent to compressing at least a portion of the data stored in the memory array.

17. The method of claim 10, further comprising:

receiving an indication to transition to an active power state; and

decompressing at least a portion of compressed data stored in the memory array responsive to receiving the indication to transition to the active power state.

18. A system comprising:

one or more memory devices to provide a memory array;

an integrated circuit coupled with the processor, the integrated circuit including compression logic to compress at least a portion of data stored in the memory array independent of an operating system;

a processor coupled with the integrated circuit; and

an antenna coupled with the processor.

19. The system of claim 18, wherein the compression logic is to compress at least a portion of the data stored in the memory array responsive at least in part to an indication from the processor to transition to a reduced power state.

20. The system of claim 19, wherein the indication to transition to the reduced power state comprises:

a command to transition to a suspend to random access memory (RAM) state.

21. The system of claim 19, wherein the compression logic further comprises:

a timer to indicate when a threshold period of time has elapsed after receiving the indication to transition to the reduced power state.

22. The system of claim 19, wherein the compression logic further comprises:

logic to individually set a power state for each memory device in the memory array.

23. The system of claim 18, wherein the integrated circuit comprises:

a memory controller.