Saving power when in or transitioning to a static mode of a processor

• US 20070294555A1
• Filed: 08/21/2007
• Published: 12/20/2007
• Est. Priority Date: 10/23/2000
• Status: Active Grant

• Current Assignee: HD Silicon Solutions LLC (f/k/a Innovative Silicon Solutions, LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Read, Andrew, Halepete, Sameer, Klayman, Keith
• Granted Patent: US 7,870,404 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Claims

1. A computer system comprising:

a processing unit;

circuitry coupled to the processor unit, said circuitry configured to provide to said processing unit;

a sleep voltage;

a first operating voltage; and

a second operating voltage that is less than the first operating voltage;

wherein said computer system has a first transition time for transitioning from said sleep voltage to said first operating voltage;

wherein said computer system has a second transition time for transitioning from said sleep voltage to said second operating voltage;

wherein said second transition time is within an allowed time for transitioning from a sleep state to an operating state; and

wherein said first transition time is greater than said allowed time.

2. A computer system as recited in claim 1 wherein said allowed time is based on a configuration of said computer system.

3. A computer system as recited in claim 1 wherein said allowed time is based on timing requirements of said computer system.

4. A computer system as recited in claim 3, wherein said timing requirements are based on interrupt response times.

5. A computer system as recited in claim 1 wherein said first and second transition times are based on respective first and second voltage ramp times.

6. A computer system as recited in claim 1 wherein said sleep voltage is sufficient to maintain state of said processing unit but is not sufficient to maintain processing activity in said processing unit.

7. A method of operating a computer processor, said method comprising:

transitioning from providing a sleep voltage to said computer processor to providing a first operating voltage to said computer processor within an allowed time for transitioning from a sleep state to an operating state; and

transitioning from said providing said first operating voltage to said computer processor to providing a second operating voltage to said computer processor, wherein a transition time for changing from said sleep voltage directly to said second operating voltage is greater than said allowed time for transitioning from said sleep state to said operating state.

8. A method in accordance with claim 7 wherein said second operating voltage is greater than said first operating voltage.

9. A method in accordance with claim 7 further comprising:

enabling a system clock to said computer processor when providing said first operating voltage to said computer processor; and

disabling said system clock to said computer processor when providing said sleep voltage to said computer processor.

10. A method in accordance with claim 7, wherein said sleep voltage is sufficient to maintain state of said computer processor but is not sufficient to maintain processing activity in said computer processor.

11. A computer system comprising:

a processor;

an adjustable voltage supply configured to output to said processor;

a sleep voltage; and

a first operating voltage that, based on a rate of transitioning from said sleep voltage to said first operating voltage, is not achievable from said sleep voltage within an allowed time for transitioning from a sleep state to an operating state.

12. A computer system as recited in claim 11, wherein said adjustable voltage supply is further configured to output to said processor a second operating voltage that, based on a rate of transitioning from said sleep voltage to said second operating voltage, is achievable from said sleep voltage within said allowed time for transitioning from said sleep state to said operating state.

13. A computer system as recited in claim 11 wherein said allowed time is based on a configuration of said computer system.

14. A computer system as recited in claim 11 wherein said adjustable voltage supply comprises a voltage regulator.

15. A computer system comprising:

a processing unit;

circuitry coupled to the processor unit, said circuitry configured to provide to said processing unit;

a first sleep voltage and a second sleep voltage;

a first operating voltage when transitioning from said first sleep voltage; and

a second operating voltage when transitioning from said second sleep voltage.

16. A computer system as recited in claim 15, wherein said circuitry is further configured to provide to said processing unit:

said first sleep voltage when transitioning from said first operating voltage; and

said second sleep voltage when transitioning from said second operating voltage.

17. A computer system as recited in claim 15 wherein a voltage difference between said first operating voltage and said first sleep voltage is approximately equal to a voltage difference between said second operating voltage and said second sleep voltage.

18. A computer system as recited in claim 15 wherein said first operating voltage is greater than said second operating voltage and wherein said first sleep voltage is greater than said second sleep voltage.

19. A computer system as recited in claim 18 wherein a voltage transition from said second sleep voltage to said first operating voltage is greater than a time allowed for transition from a sleep state to an operating state of said computer system.