Techniques for hardware-assisted multi-threaded processing
First Claim
1. An apparatus for processing a thread of a plurality of threads that share a core processor, comprising:
- an instruction random access memory (IRAM) for storing one or more sequences of instructions;
a bank of registers for storing data that is used as operands and results of the one or more series of instructions for a plurality of threads, said bank of registers including a bank address input for accessing a register in the bank of registers;
a thread ID input channel that has a width of T bits for receiving data that indicates a current thread identifier (ID) of a plurality of up to 2T threads, said thread ID input channel connected to T bits of the bank address input; and
a core processor for executing the one or more sequences of instructions for a current thread of the plurality of threads by accessing contents of a register for up to 2c registers for the current thread in the bank of registers; and
a core register access channel with a width of C bits, which connects the core processor to C bits of the bank address input different from the T bits to which the thread ID input channel is connected,wherein.the bank of registers includes 2(C+T) registers,the bank address input includes a number C+T bits, andan intra-thread register indicated by the core processor has an intra-thread address that has C bits,whereby, for a particular intra-thread register indicated on the core register access channel, a particular register accessed by the bank address input holds data that indicates contents for the particular intra-thread register for a thread having the current thread ID,
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Abstract
Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2T threads. A particular register is accessed in a register bank that has 2(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.
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Citations
32 Claims
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1. An apparatus for processing a thread of a plurality of threads that share a core processor, comprising:
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an instruction random access memory (IRAM) for storing one or more sequences of instructions; a bank of registers for storing data that is used as operands and results of the one or more series of instructions for a plurality of threads, said bank of registers including a bank address input for accessing a register in the bank of registers; a thread ID input channel that has a width of T bits for receiving data that indicates a current thread identifier (ID) of a plurality of up to 2T threads, said thread ID input channel connected to T bits of the bank address input; and a core processor for executing the one or more sequences of instructions for a current thread of the plurality of threads by accessing contents of a register for up to 2c registers for the current thread in the bank of registers; and a core register access channel with a width of C bits, which connects the core processor to C bits of the bank address input different from the T bits to which the thread ID input channel is connected, wherein. the bank of registers includes 2(C+T) registers, the bank address input includes a number C+T bits, and an intra-thread register indicated by the core processor has an intra-thread address that has C bits, whereby, for a particular intra-thread register indicated on the core register access channel, a particular register accessed by the bank address input holds data that indicates contents for the particular intra-thread register for a thread having the current thread ID, - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for processing a thread of a plurality of threads that share a core processor, comprising the steps of:
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receiving, from a core processor, a intra-thread register address that contains a core number C of bits for accessing each register of 2C registers available to each thread of a plurality of threads; receiving, from a thread scheduler component external to the core processor, a thread identifier (ID) that contains a thread ID number T of bits for indicating a particular thread in a plurality of up to 2T threads; and accessing, in a computer-readable medium configured as register bank that has 2(C+T) registers, a particular register that has an inter-thread address that includes both the intra-thread register address and the thread ID, wherein the particular register holds data that indicates contents for the intra-thread register address for a thread having the thread ID, whereby register contents of all registers of all threads reside in the register bank. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus for processing a thread of a plurality of threads that share a core processor, comprising:
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means for receiving, from a core processor, a intra-thread register address that contains a core number C of bits for accessing each register of 2C registers available to each thread of a plurality of threads; means for receiving, from a thread scheduler component external to the core processor, a thread identifier (ID) that contains a thread ID number T of bits for indicating a particular thread in a plurality of up to 2T threads; and means for accessing, in a computer-readable medium configured as register bank that has 2(C+T) registers, a particular register that has an inter-thread address that includes both the intra-thread register address and the thread ID, wherein the particular register holds data that indicates contents for the intra-thread register address for a thread having the thread ID, whereby register contents of all registers of all threads reside in the register bank.
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22. A method at a core processor for switching between threads of a plurality of processing threads that share the core processor, comprising the steps of:
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sending a prepare-to-switch signal to a first block external to the core processor while executing instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);
, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;in response to sending the prepare-to-switch signal, receiving from the first block a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor; and after sending the prepare-to-switch signal, performing the steps of sending a thread switch signal to a second block external to the core processor; and retrieving a next instruction from the next thread instruction location in the IRAM. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A method at a thread scheduler external to a core processor for switching between threads of a plurality of processing threads that share the core processor, comprising the steps of:
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receiving a prepare-to-switch signal from a core processor while the core processor executes instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);
, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;storing the current thread revival instruction location in association with a thread ID for the current processing thread in a data structure for a plurality of up to 2T processing threads that share the core processor; and in response to receiving the prepare-to-switch signal, performing the steps of determining a next processing thread of the plurality of up to 2T processing threads to be executed on the core processor, retrieving from the data structure a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor, and sending the next thread instruction location to the core processor. - View Dependent Claims (29, 30, 31)
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32. A computer-readable medium carrying one or more sequences of instructions for switching between threads of a plurality of processing threads that share a core processor, wherein execution of the one or more sequences of instructions by the core processor causes the core processor to perform the steps of:
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sending a prepare-to-switch signal to a first block external to the core processor while executing instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);
, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;in response to sending the prepare-to-switch signal, receiving from the first block a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor; and after sending the prepare-to-switch signal, performing the steps of sending a thread switch signal to a second block external to the core processor; and retrieving a next instruction from the next thread instruction location in the IRAM.
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Specification