Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement

• US 20070295948A1
• Filed: 06/07/2006
• Published: 12/27/2007
• Est. Priority Date: 06/07/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc., Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Lam, Chung Hon, Schrott, Alejandro Gabriel
• Granted Patent: US 7,473,921 B2
• Time in Patent Office: Days
• US Class Current: 257/4
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

Claims

1. A memory cell comprising:

a first feature;

a second feature, the second feature comprising a dielectric material and defining an opening at least partially overlying the first feature;

a third feature, the third feature formed on the first feature and partially filling the opening in the second feature; and

phase change material, the phase change material at least filling a volume between the second feature and the third feature;

wherein at least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

2. The memory cell of claim 1, wherein the third feature comprises a second material.

3. The memory cell of claim 2, wherein the first feature comprises an electrical conductor.

4. The memory cell of claim 2, wherein the portion of the phase change material operative to switch between lower and higher electrical resistance states is substantially located within the volume between the second feature and the third feature.

5. The memory cell of claim 1, wherein the third feature comprises an electrically conductive material.

6. The memory cell of claim 5, wherein the portion of the phase change material operative to switch between lower and higher electrical resistance states is substantially located near a surface of the third feature opposite to that formed on the first feature.

7. The memory cell of claim 5, wherein the first feature comprises a phase change material having a composition different from that of the phase change material filling the volume between the second feature and the third feature.

8. The memory cell of claim 5, wherein the phase change material filling the volume between the second feature and the third feature has a higher electrical resistivity than the electrical conductor forming the third feature.

9. The memory cell of claim 1, wherein the phase change material comprises germanium, antimony, sulfur, selenium or tellurium, or a combination thereof.

10. The memory cell of claim 1, wherein the phase change material comprises a ternary alloy comprising germanium, antimony and tellurium.

11. The memory cell of claim 1, wherein the phase change material comprises a transition metal oxide.

12. The memory cell of claim 1, wherein the first feature comprises titanium nitride or tantalum nitride, or a combination thereof.

13. The memory cell of claim 1, wherein a minimum width of the third feature is less than a prescribed minimum lithographic dimension.

14. The memory cell of claim 1, wherein the third feature is substantially circular or substantially elliptical in a plane parallel to a plane defined by the interface of the third feature and the first feature.

15. The memory cell of claim 1, wherein the third feature is substantially columnar.

16. The memory cell of claim 1, further comprising a plurality of electrodes, the electrodes operative to allow the application of the switching signal to the memory cell.

17. An integrated circuit comprising one or memory cells, at least one of the memory cells comprising:

a first feature;

a second feature, the second feature comprising a dielectric material and defining an opening at least partially overlying the first feature;

a third feature, the third feature formed on the first feature and partially filling the opening in the second feature; and

phase change material, the phase change material at least filling a volume between the second feature and the third feature;

wherein at least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

18. The integrated circuit of claim 17, wherein the integrated circuit comprises a nonvolatile memory.

19. The integrated circuit of claim 17, wherein the integrated circuit comprises a random access memory.

20. A method of forming a memory cell, the method comprising the steps of:

forming a first feature;

forming a second feature, the second feature comprising a dielectric material and defining an opening at least partially overlying the first feature;

forming a third feature, the third feature formed on the first feature and partially filling the opening in the second feature; and

forming phase change material, the phase change material at least filling a volume between the second feature and the third feature;

wherein at least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.