Semiconductor device structure for reducing mismatch effects

• US 20070296013A1
• Filed: 06/26/2006
• Published: 12/27/2007
• Est. Priority Date: 06/26/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chung-Long, Chao, Chih-Ping, Chen, Chia-Yi
• Granted Patent: US 8,330,251 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.

Claims

1. An integrated circuit chip comprising:

a first electronic device comprising a first feature, the first electronic device having a first footprint area in a given layer;

a second electronic device comprising a second feature, the second electronic device having a second footprint area in the given layer, and the first and second electronic devices being electrically matched; and

a common electrode feature that is common to the first and second electronic devices, the common electrode feature being at least partially located in the given layer,

wherein more than a majority of the first footprint area overlaps with the second footprint area,

wherein a first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature, and

wherein the first spacing is less than about three times a width of the common electrode feature.

2. The integrated circuit chip of claim 1, wherein the first and second electronic devices are capacitors.

3. The integrated circuit chip of claim 2, wherein the common electrode feature is part of a ground electrode shared by the first and second electronic devices, wherein the first feature is an inner-most finger of a positive electrode for the first electronic device, and wherein the second feature is an inner-most finger of a positive electrode for the second electronic device.

4. The integrated circuit chip of claim 2, wherein the first and second electronic devices are interdigitated capacitors.

5. The integrated circuit chip of claim 1, wherein the common electrode feature has a shaped selected from the group consisting of a cross shape, an X shape, a T shape, a straight line shape, a curved shape, a spiral shape, an S shape, a Z shape, a repeated S shape, a repeated Z shape, and combinations thereof.

6. An integrated circuit chip comprising:

a first electronic device comprising a first feature in a given layer;

a second electronic device comprising a second feature in the given layer, the first and second electronic devices being electrically matched; and

a common electrode feature that is common to the first and second electronic devices, the common electrode feature being at least partially located in the given layer,

wherein a first spacing between the first feature and the common electrode feature, and a second spacing between the second feature and the common electrode feature, each is less than about three times a width of the common electrode feature.

7. The integrated circuit chip of claim 6, wherein the first and second electronic devices are capacitors.

8. The integrated circuit chip of claim 7, wherein the common electrode feature is part of a ground electrode shared by the first and second electronic devices, wherein the first feature is an inner-most finger of a positive electrode for the first electronic device, and wherein the second feature is an inner-most finger of a positive electrode for the second electronic device.

9. The integrated circuit chip of claim 7, wherein the first and second electronic devices are interdigitated capacitors.

10. The integrated circuit chip of claim 6,

wherein the first electronic device has a first footprint area in the given layer,

wherein the second electronic device has a second footprint area in the given layer, and

wherein more than a majority of the first footprint area overlaps with the second footprint area.

11. The integrated circuit chip of claim 6, wherein the common electrode feature has a shaped selected from the group consisting of a cross shape, an X shape, a T shape, a straight line shape, a curved shape, a spiral shape, an S shape, a Z shape, a repeated S shape, a repeated Z shape, and combinations thereof.

12. An integrated circuit chip comprising:

a first interdigitated capacitor device comprising a first set of electrode fingers in a given layer;

a second interdigitated capacitor device comprising a second set of electrode fingers in the given layer; and

a common electrode shared by the first and second capacitors, the common electrode comprising a set of common electrode fingers in the given layer,

wherein at least one of the first set of electrodes is adjacent to a certain one of the common electrode fingers and separated by a first distance,

wherein at least one of the second set of electrodes is adjacent to the certain one of the common electrode fingers and separated by a second distance,

wherein the first distance is less than about 20% greater than the second distance, and

wherein the second distance is less than about 20% greater than the first distance.

13. The integrated circuit chip of claim 12, wherein each of the first set of electrode fingers is adjacent to at least one of the common electrode fingers.

14. The integrated circuit chip of claim 12, wherein each of the second set of electrode fingers is adjacent to at least one of the common electrode fingers.

15. The integrated circuit chip of claim 12,

wherein the first capacitor device has a first footprint area in the given layer,

wherein the second capacitor device has a second footprint area in the given layer, and

wherein more than a majority of the first footprint area overlaps with the second footprint area.

16. The integrated circuit chip of claim 12, wherein at least a portion of the set of common electrode fingers, has a shape selected from the group consisting of a cross shape, an X shape, a T shape, a straight line shape, a curved shape, a spiral shape, an S shape, a Z shape, a repeated S shape, a repeated Z shape, and combinations thereof, wherein such portion comprises the certain one of the common electrode fingers.