Semiconductor component and method of manufacture

• US 20070296077A1
• Filed: 06/27/2006
• Published: 12/27/2007
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Moline, Dan
• Granted Patent: US 7,605,451 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29199 Material of the matrix
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

In various embodiments, semiconductor components and methods to manufacture semiconductor components are disclosed. In one embodiment, a method to manufacture semiconductor components includes attaching multiple heat spreaders to a semiconductor wafer. Other embodiments are described and claimed.

Claims

1. A method to manufacture semiconductor components, comprising:

attaching a plurality of heat spreaders to a semiconductor wafer.

2. The method of claim 1, wherein the semiconductor wafer includes a plurality of semiconductor die, wherein each semiconductor die comprises a discrete radio frequency (RF) power transistor, and wherein each semiconductor die has a gate interconnect on a first surface of the semiconductor die, a source interconnect on the first surface of the semiconductor die, and a drain interconnect on a second surface of the semiconductor die opposite to the first surface.

3. The method of claim 2, wherein the attaching includes mounting at least one heat spreader to at least one source interconnect of at least one semiconductor die and wherein the at least one heat spreader is mounted on the at least one semiconductor die so that that the edges of the at least one heat spreader are spaced apart from the edges of the at least one semiconductor die.

4. The method of claim 1, wherein the attaching the plurality of heat spreaders to the semiconductor wafer includes bonding the plurality of heat spreaders to the semiconductor wafer.

5. The method of claim 1, wherein the attaching the plurality of heat spreaders to the semiconductor wafer includes using eutectic bonding to bond the plurality of heat spreaders to the semiconductor wafer.

6. The method of claim 1, wherein the attaching includes using heat, pressure, and motion to attach the plurality of heat spreaders to the semiconductor wafer, wherein the semiconductor wafer comprises silicon (Si) or gallium arsenide (GaAs).

7. The method of claim 1, further including cutting the semiconductor wafer to form a plurality of semiconductor die, wherein each semiconductor die comprises a vertical power transistor having a source region and a drain region that are at opposite surfaces of the semiconductor die and wherein at least one heat spreader is attached to each semiconductor die.

8. The method of claim 7,

further including attaching a first semiconductor die of the plurality of semiconductor die to a leadframe using heating;

wherein a first heat spreader of the plurality of heat spreaders is attached to the first semiconductor die;

wherein the first semiconductor die is attached to the leadframe at a relatively lower temperature than the temperature at which the first heat spreader is attached to the semiconductor die; and

wherein the vertical power transistor of the first semiconductor die is a radio frequency (RF) power transistor adapted to operate at frequencies greater than about 500 megahertz (MHz) and has a power output greater than about five watts.

9. The method of claim 8,

wherein the leadframe includes a gate lead and a drain lead;

wherein the first semiconductor die has at least one gate wafer bump coupled to a gate electrode of the first semiconductor die, at least one source wafer bump coupled to the source region of the first semiconductor die, and at least one drain interconnect coupled to the drain region of the first semiconductor die; and

further comprising coupling the gate lead of the leadframe to the at least one gate wafer bump of the first semiconductor die.

10. The method of claim 9, wherein the gate lead has a raised portion and wherein the coupling includes coupling the raised portion of the gate lead of the leadframe to the at least one gate wafer bump of the first semiconductor die using tape automated bonding (TAB).

11. The method of claim 9, wherein the gate lead has a raised portion and wherein the coupling includes coupling the raised portion of the gate lead of the leadframe to the at least one gate wafer bump of the first semiconductor die using wire bonding.

12. The method of claim 11, wherein the wire bonding includes coupling the raised portion of the gate lead of the leadframe to the at least one gate wafer bump of the first semiconductor die using a plurality of wire bonds and further comprising encapsulating the first semiconductor die, a portion of the gate lead, a portion of the first heat spreader, and a portion of the drain lead using a plastic mold compound, wherein the plastic mold compound is formed between the first semiconductor die and the plurality of wire bonds and wherein the plastic mold compound is formed between a portion of the first semiconductor die and a portion of the first heat spreader.

13. The method of claim 12, further comprising bending the gate lead and the drain lead, so that a surface of the gate lead is substantially coplanar to a surface of the drain lead and a surface of the heat spreader.

14. A discrete semiconductor component having a first terminal and a second terminal, comprising:

a semiconductor chip having a first interconnect and a second interconnect; and

a tape automated bonding (TAB) interconnect, wherein the first terminal of the discrete semiconductor component is coupled to the first interconnect of the semiconductor chip using the TAB interconnect.

15. The discrete semiconductor component of claim 14, wherein the TAB interconnect comprises a flexible dielectric material and a plurality of conductive traces formed on one side of the flexible dielectric material.

16. The discrete semiconductor component of claim 15, wherein the flexible dielectric material comprises polyimide and the plurality of conductive traces comprise copper.

17. The discrete semiconductor component of claim 14,

wherein the second interconnect of the semiconductor chip is coupled to the second terminal of the semiconductor component;

wherein the semiconductor chip comprises a discrete vertical power transistor having a gate electrode adjacent a first surface of the semiconductor chip, a source region adjacent the first surface of the semiconductor chip, and a drain region adjacent a second surface of the chip opposite to the first surface;

wherein the first interconnect is a gate interconnect coupled to the gate electrode of the semiconductor chip, the second interconnect is a drain interconnect coupled to the drain region of the semiconductor chip;

wherein the semiconductor chip has a third interconnect that is a source interconnect; and

wherein the source interconnect is coupled to the source region of the semiconductor chip.

18. The discrete semiconductor component of claim 17, further comprising a heat spreader coupled to the third interconnect of the semiconductor chip.

19. The discrete semiconductor component of claim 18, wherein the heat spreader is smaller than the semiconductor chip and wherein the heat spreader is mounted on the semiconductor chip so that the edges of the heat spreader are spaced apart from the edges of the semiconductor chip.

20. The discrete semiconductor component of claim 18, further comprising an underfill dielectric material between the heat spreader and the semiconductor chip.

21. The discrete semiconductor component of claim 18, wherein the heat spreader is rectangular shaped, the semiconductor chip is rectangular shaped, and wherein a length of the heat spreader is less than a length of the semiconductor chip and a width of the heat spreader is less than a width of the semiconductor chip.

23. The discrete semiconductor component of claim 18, further comprising a plastic packaging material encapsulating the semiconductor chip, a portion of the first terminal, a portion of the second terminal, and a portion of the heat spreader.

24. The discrete semiconductor component of claim 23, wherein the discrete semiconductor component is a surface mount device and wherein a surface of the first terminal is substantially coplanar to a surface of the second terminal and a surface of the heat spreader.

25. The discrete semiconductor component of claim 14, wherein the semiconductor chip comprises a discrete radio frequency (RF) power transistor constructed to operate at frequencies greater than about 500 megahertz (MHz) and have an output power greater than about five watts.

26. A method to manufacture a discrete semiconductor component having a gate lead, a source lead, and a drain lead, comprising:

coupling a gate pad of a semiconductor die to the gate lead of the discrete semiconductor component using tape automated bonding (TAB), wherein the semiconductor die comprises a discrete power transistor.

27. The method of claim 26, further comprising coupling a heat spreader to the semiconductor die prior to singulating the semiconductor die from a semiconductor wafer, wherein the heat spreader is the source lead.

28. The method of claim 27, further comprising forming a plastic material around the first semiconductor die and contacting a portion of the gate lead, a portion of the drain lead, and a portion of the heat spreader.

29. A discrete radio frequency (RF) power transistor, comprising:

a semiconductor chip;

a gate terminal coupled to the semiconductor chip, a source terminal coupled to the semiconductor chip, a first drain terminal coupled to the semiconductor chip, and a second drain terminal coupled to the semiconductor chip;

a plastic packaging material encapsulating the semiconductor chip, a portion of the gate terminal, a portion of the source terminal, a portion of the first drain terminal, and a portion of the second drain terminal.

30. The discrete RF power transistor of claim 29, further comprising a third drain terminal coupled to the semiconductor chip.

31. The discrete RF power transistor of claim 29, wherein the discrete RF power transistor is a surface mount device (SMD).

32. The discrete RF power transistor of claim 29,

wherein the source terminal is a heat spreader;

wherein the heat spreader is rectangular shaped and the semiconductor chip is rectangular shaped; and

wherein a length of the heat spreader is less than a length of the semiconductor chip and a width of the heat spreader is less than a width of the semiconductor chip.

35. The discrete RF power transistor of claim 29, wherein the semiconductor chip comprises a vertical power transistor having a source region and a drain region that are at opposite surfaces of the semiconductor chip and wherein the source terminal is coupled to the source region and the first and second drain terminals are coupled to the drain region.

36. A semiconductor assembly, comprising:

a metal-ceramic package; and

a semiconductor component having a plastic package mounted within the metal-ceramic package, wherein the semiconductor component is a discrete power transistor.

37. The semiconductor assembly of claim 36, wherein the semiconductor component has a semiconductor die, a gate lead coupled to the semiconductor die, a drain lead coupled to the semiconductor die, and a heat spreader coupled to the semiconductor die and wherein the metal-ceramic package has a gate lead coupled to the gate lead of the semiconductor component, a drain lead coupled to the drain lead of the semiconductor component, and a flange coupled to the heat spreader.